CLASS SSTL Search Results

DP U1

Abstract: IO317 AX1000
Contextual Info: Advanced v1.5  Axcelerator Family FPGAs Leading-Edge Performance • • • • – Voltage-Referenced I/O Standards: GTL+, HSTL Class 1, SSTL2 Class 1 and 2, SSTL3 Class 1 and 2 – Registered I/Os with 64-bit Deep FIFO on Each Pin "PerPin FIFO" – Hot-Swap Compliant I/Os (Except PCI)

AX1000

Contextual Info: Advanced v1.3  Axcelerator Family FPGAs Leading-Edge Performance • • • • – Voltage-Referenced I/O Standards: GTL+, HSTL Class 1, SSTL2 Class 1 and 2, SSTL3 Class 1 and 2 – Registered I/Os with 64-bit Deep FIFO on Each Pin "PerPin FIFO" – Hot-Swap Compliant I/Os (Except PCI)

AK 1022

Abstract: AF2.5 din 74 FIFO64K36 V123A AX1000
Contextual Info: Advanced v1.2  Axcelerator Family FPGAs Leading-Edge Performance • • • • – Voltage-Referenced I/O Standards: GTL+, HSTL Class 1, SSTL2 Class 1 and 2, SSTL3 Class 1 and 2 – Registered I/Os with 64-bit Deep FIFO on Each Pin "PerPin FIFO" – Hot-Swap Compliant I/Os (Except PCI)

v1493a

Abstract: AK 1022
Contextual Info: Advanced v1.4  Axcelerator Family FPGAs Leading-Edge Performance • • • • – Voltage-Referenced I/O Standards: GTL+, HSTL Class 1, SSTL2 Class 1 and 2, SSTL3 Class 1 and 2 – Registered I/Os with 64-bit Deep FIFO on Each Pin "PerPin FIFO" – Hot-Swap Compliant I/Os (Except PCI)

dunlop s 708

Abstract: PTI 30 040 ga AX125 AX2000 CS180 FG256 FG324 FG484 PQ208 M33 thermal fuse
Contextual Info: Advanced v1.5  Axcelerator Family FPGAs Le adi n g- E dg e P e rfo r ma nc e • • • • – Voltage-Referenced I/O Standards: GTL+, HSTL Class 1, SSTL2 Class 1 and 2, SSTL3 Class 1 and 2 – Registered I/Os with 64-bit Deep FIFO on Each Pin "PerPin FIFO"

SSTL-2

Abstract: BB1110B BB1110B13 BB1110B7 BB1110TB BB2110DI
Contextual Info: 4200 Bonita Place, Fullerton, CA 92635 BB1110TB, BB1110TB AND BB2110DI DDR SDRAM TERMINATOR NETWORKS. DESCRIPTION This “BB” family of networks is for terminating SSTL_2 Class I and Class II systems, such as DDR SDRAM. These specialty networks employ solder

RT2404B7

Abstract: RT2460B7 RT2405B7 RT2400 CTS RESISTOR NETWORK 761 RT1400B7 RT2465B7 RT1400B6 RT1401B6 RT1401B7
Contextual Info: DDR SDRAM Terminator Technical Data Sheet RoHS Compliant Parts Available Description Features This SSTL_2 terminator network provides high performance resistor termination for SSTL_2 Class I or Class II systems. • • • • • • • Designed with a ceramic substrate, this device minimizes

BB110B

Abstract: BB1110B BB1110B13 BB1110B7 BB2110DI TAPE AND REEL BGA
Contextual Info: 4200 Bonita Place, Fullerton, CA 92635 BB1110B AND BB2110DI -DDR SRAM TERMINATOR NETWORKS. DESCRIPTION The BB110B and BB2110DI are BGA Resistor Networks designed to terminate SSTL_2 Class I and Class II systems. These Networks use thick film resistors with high temperature solder balls. The resistors are integrated

SN74SSTL32877

Contextual Info: SN74SSTL32877 26-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS DESIGN GOAL DESIGN GOAL SCES241A – APRIL 1999 – REVISED MAY 1999 D Member of the Texas Instruments D D D D Differential CLK Signal D Meets SSTL_2 Class I and Class II Widebus Family

SSTL

Abstract: BI-Tech double diode parallel BB1110B BB1110B13 BB1110B7 BB1110TB BB2110DI
Contextual Info: 4200 Bonita Place, Fullerton, CA 92635 BB1110TB, BB1110B AND BB2110DI DDR SDRAM TERMINATOR NETWORKS. DESCRIPTION This “BB” family of networks is for terminating SSTL_2 Class I and Class II systems, such as DDR SDRAM. These specialty networks employ solder balls for surface mount flip chip attachment. Their

BB1110B7

Abstract: BB1110B13
Contextual Info: 4200 Bonita Place, Fullerton, CA 92635 BB1110B AND BB2110DI -DDR SRAM TERMINATOR NETWORKS. DESCRIPTION Networks are designed to terminate SSTL_2 Class I and Class II systems. Networks use thick film resistors with high temperature solder balls. With solder balls on resistor side no via connection and ceramic substrate

ICSSSTV16857

Contextual Info: ICSSSTV16857 Integrated Circuit Systems, Inc. Preliminary Product Preview DDR 14-Bit Registered Buffer Recommended Application: DDR Memory Modules Product Features: • Differential clock signal • Meets SSTL_2 signal data • Supports SSTL_2 class I & II specifications

Contextual Info: ICSSSTV16857 Integrated Circuit Systems, Inc. Preliminary Product Preview DDR 14-Bit Registered Buffer Recommended Application: DDR Memory Modules Product Features: • Differential clock signal • Meets SSTL_2 signal data • Supports SSTL_2 class I & II specifications

ICSSSTV16857

Contextual Info: ICSSSTV16857 Integrated Circuit Systems, Inc. Preliminary Product Preview DDR 14-Bit Registered Buffer Recommended Application: DDR Memory Modules Product Features: • Differential clock signal • Meets SSTL_2 signal data • Supports SSTL_2 class I & II specifications

ICSSSTV16857C

Contextual Info: Integrated Circuit Systems, Inc. ICSSSTV16857C DDR 14-Bit Registered Buffer Recommended Application: DDR Memory Modules Product Features: • Differential clock signal • Meets SSTL_2 signal data • Supports SSTL_2 class I & II specifications • Low-voltage operation

Contextual Info: Integrated Circuit Systems, Inc. ICSSSTV16857 DDR 14-Bit Registered Buffer Recommended Application: DDR Memory Modules Product Features: • Differential clock signal • Meets SSTL_2 signal data • Supports SSTL_2 class I & II specifications • low-voltage operation

Contextual Info: Integrated Circuit Systems, Inc. ICSSSTV16857C DDR 14-Bit Registered Buffer Recommended Application: DDR Memory Modules Product Features: • Differential clock signal • Meets SSTL_2 signal data • Supports SSTL_2 class I & II specifications • low-voltage operation

Contextual Info: Integrated Circuit Systems, Inc. ICSSSTV16857C DDR 14-Bit Registered Buffer Recommended Application: DDR Memory Modules Product Features: • Differential clock signal • Meets SSTL_2 signal data • Supports SSTL_2 class I & II specifications • Low-voltage operation

ICSSSTV16857

Contextual Info: Integrated Circuit Systems, Inc. ICSSSTV16857 DDR 14-Bit Registered Buffer Recommended Application: DDR Memory Modules Product Features: • Differential clock signal • Meets SSTL_2 signal data • Supports SSTL_2 class I & II specifications • low-voltage operation

KM416S4031BT-G8

Contextual Info: KM416S4031B CMOS SDRAM 1M x 16Bit x 4 Banks Synchronous DRAM with SSTL interface FEATURES GENERAL DESCRIPTION •JEDEC standard 3.3V power supply •SSTL_3 Class II compatible with multiplexed address •Four banks operation •MRS cycle with address key programs

KM416S4030AT

Abstract: ZX-03 KM416S4030AT-G
Contextual Info: KM416S4030AT SDRAM ELECTRONICS 1M x 16Bitx 4 Bank Synchronous DRAM FEATURES GENERAL DESCRIPTION • JEDEC standard 3.3V Power Supply. • LVTTL/SSTL_3 Class II compatible with multiplexed address. • 4 banks operation. • MRS cycle with address key programs.

Contextual Info: KM416S1020BT SDRAM ELECTRONICS 512K x 16B itx2 Bank Synchronous DRAM FEATURES GENERAL DESCRIPTION • JEDEC standard 3.3V Power Supply. • LVTTL/SSTL_3 Class II compatible with multiplexed address. • Dual banks operation. • MRS cycle with address key programs.

KM416S4020

Abstract: KM416S4020AT-G
Contextual Info: KM416S4020AT SDRAM ELECTRONICS 2M x 16Bitx 2 Bank Synchronous DRAM FEATURES GENERAL DESCRIPTION • JEDEC standard 3.3V Power Supply. • LVTTL/SSTL_3 Class II compatible with multiplexed address. • Dual banks operation. • MRS cycle with address key programs.

Contextual Info: Preliminary KM416S1021C CMOS SDRAM 512Kx 16Bitx 2 Banks Synchronous DRAM with SSTL interface FEATURES GENERAL DESCRIPTION • JEDEC standard 3.3V power supply > SSTL_3 Class II compatible with multiplexed address • Dual banks operation • MRS cycle with address key programs