SSTL Search Results

Contextual Info: SN74CBTLV3857 LOW-VOLTAGE 10-BIT FET BUS SWITCH WITH INTERNAL PULLDOWN RESISTORS SCDS085C – OCTOBER 1998 – REVISED MAY 2000 D D D D D D D D DBQ, DGV, DW, OR PW PACKAGE TOP VIEW Enable Signal Is SSTL_2 Compatible Flow-Through Architecture Optimizes PCB

Contextual Info: Preliminary Datasheet 1.5A DDR TERMINATION REGULATOR AP2301 General Description Features The AP2301 linear regulator is designed to meet the JEDEC specification SSTL-2 and SSTL-18 for termination of DDR-SDRAM. The regulator can sink or source up to 1.5A current continuously, offers enough

Contextual Info: SN74SSTV16857 14ĆBIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS SCES344E – DECEMBER 2000 – REVISED NOVEMBER 2002 D Member of the Texas Instruments D D D D D D D D DGG PACKAGE TOP VIEW Widebus Family Supports SSTL_2 Data Inputs Outputs Meet SSTL_2 Class II

A115-A

Abstract: C101 SN74SSTU32864D SN74SSTU32864DGKER TOP-SIDE MARKING H2 SU864D
Contextual Info: SN74SSTU32864D 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES623A – FEBRUARY 2005 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout

A115-A

Abstract: C101 SN74SSTV32877 SN74SSTV32877GKER
Contextual Info: SN74SSTV32877 26-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS SCES378B – OCTOBER 2001 – REVISED MAY 2002 D D D D D D Member of the Texas Instruments Widebus+ Family Supports SSTL_2 Data Inputs Outputs Meet SSTL_2 Class II Specifications Differential Clock Inputs CLK and CLK

Contextual Info: LP2998/LP2998-Q1 www.ti.com SNVS521J – DECEMBER 2007 – REVISED DECEMBER 2013 LP2998/LP2998-Q1 DDR-I and DDR-II Termination Regulator Check for Samples: LP2998/LP2998-Q1 FEATURES DESCRIPTION • The LP2998 linear regulator is designed to meet JEDEC SSTL-2 and JEDEC SSTL-18 specifications

Contextual Info: SSTL16857 14-bit SSTL_2 Registered Buffer HITACHI ADE-205-223B Z Preliminary 3rd. Edition February 1999 Description The SSTL16857 is a 14-bit registered buffer designed for 2.3 V to 3.6 V Vcc operation and LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input.

Contextual Info: HM5425161B Series HM5425801B Series HM5425401B Series 256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword x 16-bit x 4-bank/8-Mword x 8-bit x 4-bank/ 16-Mword x 4 -bit x 4 -bank HITACHI ADE-203-1077 Z Preliminary Rev. 0.0 Jun. 28, 1999

SN74CBTLV3857

Abstract: SN74CBTLV3857DBQR SN74CBTLV3857DGVR SN74CBTLV3857DW SN74CBTLV3857DWR SN74CBTLV3857PWR
Contextual Info: SN74CBTLV3857 LOW-VOLTAGE 10-BIT FET BUS SWITCH WITH INTERNAL PULLDOWN RESISTORS SCDS085D – OCTOBER 1998 – REVISED MARCH 2001 D D D D D D D DBQ, DGV, DW, OR PW PACKAGE TOP VIEW Enable Signal Is SSTL_2 Compatible Flow-Through Architecture Optimizes PCB

SN74SSTL16847

Contextual Info: SSTL16847 20-BIT SSTL_3 INTERFACE BUFFER WITH 3-STATE OUTPUTS SCBS709A – OCTOBER 1997 – REVISED MAY 1998 D D D D D D D DGG PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family Supports SSTL_3 Signal Inputs and Outputs Flow-Through Architecture Optimizes PCB

D869

Abstract: marking nb IDT74SSTU32D869
Contextual Info: IDT74SSTU32D869 14-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE 14-BIT 1:2 REGISTERED BUFFER WITH PARITY IDT74SSTU32D869 FEATURES: • • • • • • • • 1.8V Operation Designed to drive low impedance nets SSTL_18 style clock and data inputs

DTM63614

Contextual Info: DTM63614 1GB-128M x 72, 184 Pin Registered DDR SDRAM DIMM Performance Range 266MHz/CL=2.5 200MHz/CL=2 Features Description Utilizes 133MHz DDR SDRAM Auto & self refresh capability SSTL_2 compatible inputs and outputs VDD/VDDQ= 2.5V +/- 0.2V MRS cycle, with address key, programs Latency Access

F-100

Abstract: ML6553 ML6553CS-1
Contextual Info: www.fairchildsemi.com ML6553 Bus Termination Regulator Features General Description • Can source and sink up to 1A • Generates termination voltages for DDR SDRAM, SSTL_2 SDRAM, SGRAM, or equivalent memories • Generates termination voltages for active termination

SSTV16857

Contextual Info: Preliminary Revised April 2000 SSTV16857 14-Bit Register with SSTL-2 Compatible I/O and Reset Preliminary General Description Features The SSTV16857 is a 14-bit register designed for use with 184 and 232 pin DDR-I memory modules. The device has a differential input clock, SSTL-2 compatible data inputs

Q1B-Q13B

Abstract: SSTV16859
Contextual Info: Revised March 2001 SSTV16859 Dual Output 13-Bit Register with SSTL-2 Compatible I/O and Reset General Description Features The SSTV16859 is a dual output 13-bit register designed for use with 184 and 232 pin DDR-1 memory modules. The device has a differential input clock, SSTL-2 compatible

SSTV16859

Contextual Info: Revised August 2001 SSTV16859 Dual Output 13-Bit Register with SSTL-2 Compatible I/O and Reset General Description Features The SSTV16859 is a dual output 13-bit register designed for use with 184 and 232 pin DDR-1 memory modules. The device has a differential input clock, SSTL-2 compatible

857l

Abstract: SY55857L SY55857LKG SY55857LKGTR SY55857LKI SY55857LKITR SY58021U
Contextual Info: Micrel, Inc. SuperLite SY55857L SuperLite™ 3.3V, 2.5Gbps ANY INPUT-to-LVPECL DUAL TRANSLATOR SY55857L FEATURES • Input accepts virtually all logic standards: • Single-ended: SSTL, TTL, CMOS • Differential: LVDS, HSTL, CML ■ Guaranteed AC parameters over temperature:

Contextual Info: CBTW28DD14 14-bit bus switch/multiplexer for DDR2/DDR3/DDR4 applications Rev. 6 — 25 July 2014 Product data sheet 1. General description This 14-bit bus switch/multiplexer MUX is designed for 1.5 V or 1.8 V supply voltage operation, POD_12, SSTL_12, SSTL_135, SSTL_15 or SSTL_18 signaling and CMOS

Contextual Info: SSTL16837A 20-BIT SSTL 3 INTERFACE UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS S C BS 675G - S E P TE M B E R 1996 - R EVISED S E P TE M B E R 1998 Member of the Texas Instruments Widebus Family DGG PACKAGE TOP VIEW Supports SSTL 3 Signal Inputs and

SPARTAN XC2S50

Abstract: SPARTAN-II SPARTAN-II xc2s100 pq208 CS144 FG256 PQ208 TQ144 VQ100 XC2S100 XC2S15
Contextual Info: Robust Feature Set • Flexible on-chip memory Distributed and Block Memory • 4 Digital Delay Lock Loops per device Efficient chip level/ board level clock management • Select I/O Technology Interface to all major bus standards HSTL, GTL, SSTL, etc…

is46dr32801a-5bbla1

Abstract: 126-ball IS46DR32801A
Contextual Info: IS43DR32800A, IS43/46DR32801A 8Mx32 256Mb DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O SSTL_18-compatible • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS)

IS43DR83200A

Abstract: IS43DR16160A-3DBLI datasheet IS43DR16160A-37CBLI IS43DR83200A-37CBLI IS43DR32160A DDR2 x32
Contextual Info: IS43DR83200A IS43/46DR16160A, IS43DR32160A 32Mx8, 16Mx16, 16Mx32 stacked die DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle

Contextual Info: SC2595 Integrated Linear DDR Termination Regulator POWER MANAGEMENT Description Features The SC2595 is an integrated linear DDR termination device which provides a complete solution for DDR termination designs while meeting the JEDEC requirements of SSTL-2 specifications for DDR-SDRAM

C 151 C

Abstract: LP2995M
Contextual Info: February 2002 LP2995 DDR Termination Regulator General Description Features The LP2995 regulator is designed to provide a linear solution to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot