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    ddr2 x32 Datasheets

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    ddr2 x32 Datasheets Context Search

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    2009 - DDR2 x32

    Abstract: K4T1G313QI-MCE7
    Text: K4T1G313QI DDR2 SDRAM 1Gb x32 I-die DDR2 SDRAM Specification 128FBGA with Lead-Free & , . 21 16.0 DDR2 ( x32 ) SDRAM EMR(# , DDR2 device is available in 128ball FBGA( x32 ) . Note : The functionality described and the timing , parameters are utilized DDR2 -800 Parameter CL(IDD) tRCD(IDD) tRC(IDD) tRRD(IDD)- x32 tCK(IDD) tRASmin(IDD) tRP , during DESELECTs. IOUT = 0mA Timing Patterns for 4bank devices x32 with 2CS - DDR2 -667 5/5/5 : A0 RA0 D


    Original     		PDF K4T1G313QI 128FBGA DDR2 x32 K4T1G313QI-MCE7

    2004 - Not Available

    Abstract: No abstract text available
    Text: ( x32 ) DDR2 ( x32 ) requires Auto Refresh cycles at an average interval of 7.8us (maximum). A maximum of , 128 32 x32 DQi Address Register iCK ADDR Column Decoder LCBR LRAS Col. Buffer , update. To guarantee optimum output driver impedance after power-up, the GDDR3( x32 ) needs 20us after the , SDRAM The DESELECT function (/CS high) prevents new commands from being executed by the DDR( x32 ). The GDDR3( x32 ) SDRAM is effectively deselected. Operations already in progress are not affected. NO


    Original     		PDF K4J55323QF-GC 256Mbit 32Bit K4J55323QF-GC12 K4J55323QF-Max

    2005 - DDR2 x32

    Abstract: GDDR3 SDRAM 256Mb K4J55323QF-GC K4J55323QF-GC12 K4J55323QF-GC14 MICRON gddr3 K4J55323QF-GC20 Gl WL02 Elpida GDDR3 T12N
    Text: the address bits a "Don't Care" during an Auto Refresh command. The 256Mb( x32 ) DDR2 ( x32 ) requires , Register iCK 2M x 32 x32 DQi 2M x 32 Column Decoder Col. Buffer LCBR LRAS , output driver impedance after power-up, the GDDR3( x32 ) needs 20us after the clock is applied and stable , commands from being executed by the DDR( x32 ). The GDDR3( x32 ) SDRAM is effectively deselected. Operations , instruct selected GDDR3( x32 ) to perform a NOP (/CS LOW). This prevents unwanted commands from being


    Original     		PDF K4J55323QF-GC 256Mbit 32Bit K4J55323QF-G DDR2 x32 GDDR3 SDRAM 256Mb K4J55323QF-GC K4J55323QF-GC12 K4J55323QF-GC14 MICRON gddr3 K4J55323QF-GC20 Gl WL02 Elpida GDDR3 T12N

    2004 - K4J55323QF-GC20

    Abstract: K4J55323QF-GC K4J55323QF-GC12 K4J55323QF-GC14 K4J55323QF-GC16 DDR2 x32 ELPIDA ddr2 RAM
    Text: . The 256Mb( x32 ) DDR2 ( x32 ) requires Auto Refresh cycles at an average interval of 7.8us (maximum). A , x32 DQi 2M x 32 Column Decoder Col. Buffer LRAS LCBR Latency & Burst Length LCKE , impedance after power-up, the GDDR3( x32 ) needs 20us after the clock is applied and stable to calibrate the , DESELECT function (/CS high) prevents new commands from being executed by the DDR( x32 ). The GDDR3( x32 , ) The NO OPERATION (NOP) command is used to instruct selected GDDR3( x32 ) to perform a NOP (/CS LOW).


    Original     		PDF K4J55323QF-GC 256Mbit 32Bit -GC12 20very K4J55323QF-GC20 K4J55323QF-GC K4J55323QF-GC12 K4J55323QF-GC14 K4J55323QF-GC16 DDR2 x32 ELPIDA ddr2 RAM

    2004 - DDR2 x32

    Abstract: GC14 K4J55323QF-GC K4J55323QF-GC12 K4J55323QF-GC14 K4J55323QF-GC16 t8n 800 ELPIDA DDR User
    Text: the address bits a "Don't Care" during an Auto Refresh command. The 256Mb( x32 ) DDR2 ( x32 ) requires , Row Decoder Refresh Counter Row Buffer ADDR Address Register iCK 2M x 32 x32 DQi , output driver impedance after power-up, the GDDR3( x32 ) needs 20us after the clock is applied and stable , commands from being executed by the DDR( x32 ). The GDDR3( x32 ) SDRAM is effectively deselected. Operations , instruct selected GDDR3( x32 ) to perform a NOP (/CS LOW). This prevents unwanted commands from being


    Original     		PDF K4J55323QF-GC 256Mbit 32Bit K4J55323QF-GC12 K4J55323QF-GC14/16/20 DDR2 x32 GC14 K4J55323QF-GC K4J55323QF-GC14 K4J55323QF-GC16 t8n 800 ELPIDA DDR User

    2005 - K4J55323QF-GC20

    Abstract: K4J55323QF-GC K4J55323QF-GC12 K4J55323QF-GC14 gddr3 Gl WL02 A/SAMSUNG GDDR3
    Text: the address bits a "Don't Care" during an Auto Refresh command. The 256Mb( x32 ) DDR2 ( x32 ) requires , Register iCK 2M x 32 x32 DQi 2M x 32 Column Decoder Col. Buffer LCBR LRAS , output driver impedance after power-up, the GDDR3( x32 ) needs 20us after the clock is applied and stable , commands from being executed by the DDR( x32 ). The GDDR3( x32 ) SDRAM is effectively deselected. Operations , instruct selected GDDR3( x32 ) to perform a NOP (/CS LOW). This prevents unwanted commands from being


    Original     		PDF K4J55323QF-GC 256Mbit K4J55323QF-GC20 K4J55323QF-GC K4J55323QF-GC12 K4J55323QF-GC14 gddr3 Gl WL02 A/SAMSUNG GDDR3

    2007 - K4J52324QC

    Abstract: K4J52324QC-bj11
    Text: specification & added package dimension Revision 0.3 (January 26, 2004) · Changed part number of 512Mb( x32 , Row Buffer Row Decoder x32 DQi Address Register iCK ADDR Column Decoder LCBR LRAS , , the GDDR3( x32 ) needs at least 20us after the clock is applied and stable to calibrate the impedance , function (/CS high) prevents new commands from being executed by the DDR( x32 ). The GDDR3( x32 ) SDRAM is , OPERATION (NOP) command is used to instruct selected GDDR3( x32 ) to perform a NOP (/CS LOW). This prevents


    Original     		PDF K4J52324QC 512Mbit r7/08/13 450KB K4J52324QC-AC200 K4J52324QC-BC140 K4J52324QC-BC200 K4J52324QC-BJ110 K4J52324QC-BJ120 K4J52324QC-BJ1A0 K4J52324QC K4J52324QC-bj11

    2006 - K4J52324Qc

    Abstract: No abstract text available
    Text: specification & added package dimension Revision 0.3 (January 26, 2004) · Changed part number of 512Mb( x32 , Row Buffer Row Decoder x32 DQi Address Register iCK ADDR Column Decoder LCBR LRAS , , the GDDR3( x32 ) needs at least 20us after the clock is applied and stable to calibrate the impedance , function (/CS high) prevents new commands from being executed by the DDR( x32 ). The GDDR3( x32 ) SDRAM is , OPERATION (NOP) command is used to instruct selected GDDR3( x32 ) to perform a NOP (/CS LOW). This prevents


    Original     		PDF K4J52324QC 512Mbit K4J52324Qc

    2002 - DDR2 x32

    Abstract: No abstract text available
    Text: Changed part number of 512Mb( x32 ) GDDR3 from K4J53324QB-GC to K4J52324QB-GC Revision 0.2 (January 5 , Buffer Row Decoder x32 DQi Address Register iCK ADDR Column Decoder LCBR LRAS Col , guarantee optimum output driver impedance after power-up, the GDDR3( x32 ) needs at least 20us after the clock , by the DDR( x32 ). The GDDR3( x32 ) SDRAM is effectively deselected. Operations already in progress are , ( x32 ) to perform a NOP (/CS LOW). This prevents unwanted commands from being registered during idle or


    Original     		PDF K4J52324QC-B 512Mbit DDR2 x32

    2006 - Not Available

    Abstract: No abstract text available
    Text: 0.3 (January 26, 2004) · Changed part number of 512Mb( x32 ) GDDR3 from K4J53324QB-GC to K4J52324QB-GC , -bit prefetch 32 Refresh Counter Row Buffer Row Decoder x32 DQi Address Register iCK ADDR , impedance after power-up, the GDDR3( x32 ) needs at least 20us after the clock is applied and stable to , function (/CS high) prevents new commands from being executed by the DDR( x32 ). The GDDR3( x32 ) SDRAM is , OPERATION (NOP) command is used to instruct selected GDDR3( x32 ) to perform a NOP (/CS LOW). This prevents


    Original     		PDF K4J52324QC-B 512Mbit

    2007 - K4J52324QE-BC12

    Abstract: No abstract text available
    Text: Register iCK 2M x 32 4-bit prefetch 2M x 32 x32 DQi 2M x 32 2M x 32 2M x 32 , impedance after power-up, the GDDR3( x32 ) needs at least 20us after the clock is applied and stable to , commands from being executed by the DDR( x32 ). The GDDR3( x32 ) SDRAM is effectively deselected. Operations , instruct selected GDDR3( x32 ) to perform a NOP (/CS LOW). This prevents unwanted commands from being , Refresh command. The 512Mb( x32 ) GDDR3 requires Auto Refresh cycles at an average interval of 3.9us


    Original     		PDF K4J52324QE 512Mbit K4J52324QE-BC12

    2008 - K4J52324QE-BJ1A

    Abstract: K4J52324QE-BC14
    Text: Counter Row Buffer Row Decoder x32 DQi Address Register iCK ADDR Column Decoder LCBR , impedance after power-up, the GDDR3( x32 ) needs at least 20us after the clock is applied and stable to , by the DDR( x32 ). The GDDR3( x32 ) SDRAM is effectively deselected. Operations already in progress are , ( x32 ) to perform a NOP (/CS LOW). This prevents unwanted commands from being registered during idle or , the address bits a "Don't Care" during an Auto Refresh command. The 512Mb( x32 ) GDDR3 requires Auto


    Original     		PDF K4J52324QE 512Mbit K4J52324QE-BJ1A K4J52324QE-BC14

    2005 - DDR RAM 512M

    Abstract: K4J52324QC-BC14 Hynix Cross Reference hynix memory h9 ddr2 K4J52324Q K4J52324QC-BJ12 mark t5n gddr3 K4J52324QC-BC20 K4J52324QC-A
    Text: package dimension Revision 0.3 (January 26, 2004) · Changed part number of 512Mb( x32 ) GDDR3 from , 4-bit prefetch 2M x 32 x32 DQi 2M x 32 2M x 32 2M x 32 Column Decoder Col. Buffer , specifications are met during update. To guarantee optimum output driver impedance after power-up, the GDDR3( x32 , commands from being executed by the DDR( x32 ). The GDDR3( x32 ) SDRAM is effectively deselected. Operations , instruct selected GDDR3( x32 ) to perform a NOP (/CS LOW). This prevents unwanted commands from being


    Original     		PDF K4J52324QC-B 512Mbit DDR RAM 512M K4J52324QC-BC14 Hynix Cross Reference hynix memory h9 ddr2 K4J52324Q K4J52324QC-BJ12 mark t5n gddr3 K4J52324QC-BC20 K4J52324QC-A

    2007 - K4J52324QE-BC12

    Abstract: K4J52324QE-BC14 K4J52324QE-BJ1A k4j52324qe K4J52324QEBC14 DDR2 x32 K4J52324Q samsung K4 ddr BJ11 WL02
    Text: x32 DQi 2M x 32 2M x 32 2M x 32 Column Decoder Col. Buffer LCBR LRAS Latency & , guarantee optimum output driver impedance after power-up, the GDDR3( x32 ) needs at least 20us after the clock , ( x32 ). The GDDR3( x32 ) SDRAM is effectively deselected. Operations already in progress are not affected. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to instruct selected GDDR3( x32 ) to perform , address bits a "Don't Care" during an Auto Refresh command. The 512Mb( x32 ) GDDR3 requires Auto Refresh


    Original     		PDF K4J52324QE 512Mbit K4J52324QE-BC12 K4J52324QE-BC14 K4J52324QE-BJ1A k4j52324qe K4J52324QEBC14 DDR2 x32 K4J52324Q samsung K4 ddr BJ11 WL02

    Samsung EOL

    Abstract: IS42S81600F is42s16320 IS43DR16320 IS42S32200L IS49NLC36800 IS43R32400E IS46R Mobile SDRAM IS42S32200E
    Text: /DDR1 16Mb-512Mb Highest density & bandwidth Mobile DRAM 16Mb-1Gb DDR2 256Mb-2Gb Long-Term , support Temperature Range: -40°C to +85°C Leaded Package Option x32 Organization Support for 5V products , industrial temperature ISSI supports leaded package as well as ROHS ISSI offers broadest range of x32 , · sram@issi.com · www.issi.com Industrial Grade Memory Products DDR2 SDRAM Product Features , · Programmable CAS Latency of 3, 4, 5 or 6 DDR2 SDRAM Ordering Options Density Config. 8Mx32 8Mx32


    Original     		PDF 288-576Mb 10-20ns 18-72Mb 64Kb-16Mb 8Mb-64Mb 16Mb-512Mb 16Mb-1Gb 256Mb-2Gb 200Mhz -40oC Samsung EOL IS42S81600F is42s16320 IS43DR16320 IS42S32200L IS49NLC36800 IS43R32400E IS46R Mobile SDRAM IS42S32200E

    2005 - DDR2 x32

    Abstract: ELPIDA DDR3 DDR3 DRAM layout ddr3 sdram chip datasheets 128mb 512MB xdr elpida DRAM elpida ELPIDA DDR2
    Text: SDRAM 800Mbps to 1600Mbps 2.7GB/s to 4.3GB/s DDR2 SDRAM ( x32 ) 667Mbps to 1066Mbps DDR2 , architectures for digital consumer devices including SDRAM, DDR SDRAM, DDR2 SDRAM and XDRTM DRAM. Digital , memory products, including SDRAM, DDR SDRAM, DDR2 SDRAM and XDR DRAM. Digital Players The digital , x16/x32bit SDRAM, DDR SDRAM and x16-bit DDR2 SDRAM. Printers Digital Video Cameras Improved , recording equipment requirements, including: SDRAM, DDR SDRAM and DDR2 SDRAM. Gaming Systems Today


    Original     		PDF x32-bit 256Mb x16-bit 229mA 258mA 172mA 256Mb 512Mb E0652E90 DDR2 x32 ELPIDA DDR3 DDR3 DRAM layout ddr3 sdram chip datasheets 128mb 512MB xdr elpida DRAM elpida ELPIDA DDR2

    IS46DR16320B

    Abstract: DDR2800D BGA84 DDR2800E DDR2-1066F IS43DR16320B BGA60 IS43DR16320 BGA-84 ddr2
    Text: 1Gb DDR2 Up to 533MHz clock speed PRODUCT FEATURES: · · · · · · · · · · Single supply voltage of , = 5) tCK (CL = 6) tCK (CL = 7) Frequency (max) -3D DDR2 -667D 5-5-5 5 3.75 3 3 3 333 -25E -25D DDR2 -800E DDR2 -800D 6-6-6 5-5-5 5 5 3.75 3.75 3 2.5 2.5 2.5 2.5 2.5 400 400 -19F DDR2 -1066F 7-7-7 5 3.75 3 2.5 1.875 533 Units tCK ns ns ns ns ns MHz ISSI DDR2 Ordering Options (Datasheets) Part No. IS43DR32800A , IS43DR16640A IS46DR16640A IS43DR81280A 1G 512M Den. Org. 8M x32 8M x32 8M x32 16M x16 16M x16 32M x8 32M x16


    Original     		PDF 533MHz 84-ball 60-ball Par84) -37CBL, -37CBLI -37CBLI, IS46DR16320B DDR2800D BGA84 DDR2800E DDR2-1066F IS43DR16320B BGA60 IS43DR16320 BGA-84 ddr2

    2006 - pc2-5300

    Abstract: elpida 1gb pc2 ECL120ACECN ELPIDA DDR2 PC2-3200 ELPIDA 68-FBGA Elpida DDR2 SDRAM component EDE1104ABSE EDE1108AASE
    Text: Selection Guide CONTENTS 1. DDR2 2. DDR2 SDRAM Module 240-pin Registered 3. DDR2 SDRAM Module 240-pin Unbuffered DIMM .5 4. DDR2 SDRAM Module 200-pin SO-DIMM , ) .9 Selection Guide E0853E70 (Ver.7.0) 3 DRAM Selection Guide 1. DDR2 SDRAM Density


    Original     		PDF E0853E70 240-pin 200-pin M01E0107 pc2-5300 elpida 1gb pc2 ECL120ACECN ELPIDA DDR2 PC2-3200 ELPIDA 68-FBGA Elpida DDR2 SDRAM component EDE1104ABSE EDE1108AASE

    DDR2 x32

    Abstract: IS43DR86400B IS43DR16320B is43dr32800a IS46DR16640A DDR2-1066F IS46DR16320B DDR2-667D BGA-60 BGA84
    Text: 512Mb DDR2 · · · · · · · · · · Up to 400MHz clock speed PRODUCT FEATURES: Single supply , = 5) tCK (CL = 6) tCK (CL = 7) Frequency (max) -37C DDR2 -533C 4-4-4 5 3.75 3.75 3.75 3.75 266 -3D DDR2 -667D 5-5-5 5 3.75 3 3 3 333 -25E DDR2 -800E 6-6-6 5 3.75 3 2.5 2.5 400 -25D DDR2 -800D 5-5-5 5 3.75 2.5 2.5 2.5 400 Units tCK ns ns ns ns ns MHz ISSI DDR2 Ordering Options (Datasheets) Part No , IS43DR86400B IS43DR16640A IS46DR16640A IS43DR81280A 1G 512M Den. Org. 8M x32 8M x32 8M x32 16M x16 16M x16 32M


    Original     		PDF 512Mb 400MHz 84-ball 60-ball -37CBL, -37CBLI -37CBLI, DDR2 x32 IS43DR86400B IS43DR16320B is43dr32800a IS46DR16640A DDR2-1066F IS46DR16320B DDR2-667D BGA-60 BGA84

    2012 - samsung ddr3 ram MTBF

    Abstract: KLM2G1HE3F-B001 KLM4G1FE3B-B001 KLMAG2GE4A-A001 k4B2G1646 KLMAG KLM8G2FE3B-B001 K4B2G0446 klm8g k4x2g323pd
    Text: • DDR3 SDRAM • DDR2 SDRAM • DDR SDRAM • SDRAM • Mobile DRAM • Graphics DDR , available in ES only K0 = DDR3-1600 (11-11-11) MA = DDR3-1866 (13-13-13) DDR2 SDRAM REGISTERED , -5300 ( DDR2 -667 @ CL=5) F7 = PC2-6400 ( DDR2 -800 @ CL=6) E7 = PC2-6400 ( DDR2 -800 @ CL=5) Now Voltage = 1.8V DDR2 SDRAM VLP REGISTERED MODULES Density Organization Part Number Composition , x4)*18 Lead free 667 Y 1 Now DDR2 SDRAM FULLY BUFFERED MODULES Density


    Original     		PDF BR-12-ALL-001 samsung ddr3 ram MTBF KLM2G1HE3F-B001 KLM4G1FE3B-B001 KLMAG2GE4A-A001 k4B2G1646 KLMAG KLM8G2FE3B-B001 K4B2G0446 klm8g k4x2g323pd

    W25R128FV

    Abstract: W25Q128JV W25R128F W25Q128FV W25Q128F USON-8 W25Q80DL W978H6KB W25Q80BVSSIG
    Text: support on SDR and DDR for portable devices. Interface •x16/ x32 SDR/DDR •x8/x16 DDR2 /DDR3 , Low Power DDR2 SDRAM Pseudo SRAM KGD Specialty DRAM 03 05 06 07 08 SDRAM DDR SDRAM DDR2 , Power DDR SDRAM Low Power DDR2 SDRAM Pseudo SRAM KGD Winbond Electronics Corporation is a leading , . Winbond mobile DRAM devices support both x16 and x32 data widths. Major features for the families of , LPDDR 128Mb - 1Gb LPDDR2 256Mb - 2Gb X16 / X32 PSRAM 64Mb- 256Mb X16 Type


    Original     		PDF

    2012 - Micron Technology

    Abstract: No abstract text available
    Text: DRAM or just DRAM (DDR, DDR2 , DDR3. etc.) JEDEC standard JESD79E, etc • LPDDRx – Referred to as , Feature Comparison Type LPDDR(1) LPDDR2 LPDDR3 DDR2 DDR3/DDR3L DDR4 Die Density , +/DDR3200+ Burst Lengths Configurations 2, 4, 8, 16 x16, x32 BC4, 8 x4, x8, x16 BC4, 8 x4, x8, x16, x32 22 pins 8 x16, x32 14 pins (Mux’d command address) 4, 8 x4, x8, x16 Address/ Command Signals 4, 8, 16 x16, x32 14 pins (Mux’d command address) 25 pins 27 pins


    Original     		PDF 20Note/DRAM/TN4102 TN-41-04: TN-41-13: TN-46-02: TN-46-06: TN-46-11: TN-46-14: TN-47-19: TN-47-20: Micron Technology

    2012 - K4X2G323PD8GD8

    Abstract: K9HFGY8S5A-HCK0 K4H511638JLCCC samsung eMMC 5.0 KLMBG4GE2A-A001 K9K8G08U0D-SIB0 K4X51163PK-FGD8 KLMAG2GE4A k4h561638n-lccc K4G10325FG-HC03
    Text: 4–12 • DDR3 SDRAM • DDR2 SDRAM • DDR SDRAM • SDRAM • Mobile DRAM • Graphics , Now Now Now Now Now Now Now Now Now Now MA = DDR3-1866 (13-13-13) DDR2 SDRAM , Now Notes: E6 = PC2-5300 ( DDR2 -667 @ CL=5) F7 = PC2-6400 ( DDR2 -800 @ CL=6) E7 = PC2-6400 ( DDR2 -800 @ CL=5) Voltage = 1.8V DDR2 SDRAM SODIMM MODULES Density Organization Part Number , )*8 Lead free 667/800 2 Now Notes: E6 = PC2-5300 ( DDR2 -667 @ CL=5) F7 = PC2


    Original     		PDF BR-12-ALL-001 K4X2G323PD8GD8 K9HFGY8S5A-HCK0 K4H511638JLCCC samsung eMMC 5.0 KLMBG4GE2A-A001 K9K8G08U0D-SIB0 K4X51163PK-FGD8 KLMAG2GE4A k4h561638n-lccc K4G10325FG-HC03

    2002 - DDR RAM 512M

    Abstract: ELPIDA mobile DDR TSOP II elpida ect-ts-1942 Elpida Memory DDR2-533 DDR2-667 DDR2-800 PC2-5300 PC2-6400
    Text: SDRAM, DDR SDRAM Module E: DDR2 , DDR2 Module Type K: DDR Mobile RAM (Bare Chip / Package) B , Decoder - 3 DDR2 E D E 11 04 A A SE - 5C - E Elpida Memory Environment Code E: Lead Free (RoHS compliant) Type D: Monolithic Device Speed 8E: DDR2 -800(5-5-5) GE: 800Mbps(5-5-5) 6C: DDR2 -667(4-4-4) 6E: DDR2 -667(5-5-5) 5C: DDR2 -533(4-4-4) 4A: DDR2 -400(3-3-3) Product Family E: DDR2 , Number Decoder - 4 DDR2 Module E B E 20 R E 4 A A F A - 5C - E Environment Code Elpida Memory


    Original     		PDF ECT-TS-1942 1200MHz 184-pin 160-pin 232-pin 1066MHz DDR RAM 512M ELPIDA mobile DDR TSOP II elpida Elpida Memory DDR2-533 DDR2-667 DDR2-800 PC2-5300 PC2-6400

    2002 - ELPIDA DDR3

    Abstract: Elpida GDDR5 elpida GDDR5 tsop ddr2 ram ELPIDA mobile DDR ELPIDA ddr2 RAM SODIMM ddr2 8gb ddr2 8gb mobile memory DDR3 DIMM elpida
    Text: Family J: DDR3 E: DDR2 D: DDR SDRAM, DDR Mobile RAM Power Supply, Interface Organization Density / Bank S: SDRAM, (SDR) Mobile RAM W: GDDR5 X: XDR B: DDR2 Mobile RAM R: RDRAM ©Elpida Memory, Inc , information) Module Outline J: DDR3 Module Die Rev. (Mono) Power Supply, Interface E: DDR2 Module , Decoder - 6 DDR2 E D E 21 04 A B SE - 5C - E Elpida Memory Environment Code E: Lead Free (RoHS compliant) F: Lead Free (RoHS compliant) and Halogen Free Type D: Monolithic Device Speed 1J: DDR2


    Original     		PDF ECT-TS-1993 16-bank 512Mb x16bit x32bit ELPIDA DDR3 Elpida GDDR5 elpida GDDR5 tsop ddr2 ram ELPIDA mobile DDR ELPIDA ddr2 RAM SODIMM ddr2 8gb ddr2 8gb mobile memory DDR3 DIMM elpida
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