CK155 Search Results

R4383

Abstract: T400 clock TSWC03622 TSYN01622 TSYN03622 TSWC01622 TSWC02622
Contextual Info: Advisory October 28, 2003 TSWC01622/TSWC02622/TSWC03622/TSYN01622/TSYN03622 Device Version 1.1 Advisory The following data sheets are to be referenced: • TSWC01622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch data sheet DS03-117HSPL-1 . ■

GR-253

Abstract: TTRN0110G
Contextual Info: Data Sheet March 29, 2002 TTRN0110G 10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer Features Applications Supports standard OC-192/STM-64 data rate of 9.95328 Gbits/s up through forward error correction FEC rate of 10.7092 Gbits/s as well as the Ethernet rate of 10.3125 Gbits/s

YA28

Abstract: AC10 post amplifier A0774011 AC10 GR-253 YA18 qmv1080 QMV108
Contextual Info: Data Sheet YA28 2.5 Gb/s 1:4 Demultiplexer with Clock and Data Recovery Features Meets or exceeds all relevant ANSI, ITU and Bellcore specifications Fully balanced, differential architecture Differential CML data input accepts signals of 2.5 Gb/s data rate

1 into 16 demultiplexer circuit diagram using 1 i

Abstract: 1 into 12 demultiplexer circuit diagram 1 into 16 demultiplexer circuit diagram ip 65 equipment qmv10 AB89 AC10 UT15 AC10 post amplifier YA18
Contextual Info: YA20 2.5 Gb/s 1:16 Demultiplexer Data Sheet Features Data and clock inputs accept differential CML signals at up to 2.5 Gb/s Internally generated divide-by-16 clock and deserialized data delivered via PECL 100 k outputs Fully differential internal logic for

CKT55

Contextual Info: DESCRIPTION FEATURES • Single chip source for 622.08M Hz and 155.52MHz clocks ■ 622.08M Hz output is differential PECL, 155.52MHz output is single-ended PECL ■ TTL/C M O S com patible inputs and reference output ■ SONET com pliant jitter perform ance <0.01 Ul

1 into 16 demultiplexer circuit diagram using 1 i

Abstract: 1 into 12 demultiplexer circuit diagram Nortel demux AB89 AC10 YA08 YA18 YA19 YA20 1 into 4 demultiplexer circuit diagram
Contextual Info: YA20 2.5 Gb/s 1:16 Demultiplexer Data Sheet Features Data and clock inputs accept differential CML signals at up to 2.5 Gb/s Internally generated divide-by-16 clock and deserialized data delivered via PECL 100 k outputs Fully differential internal logic for

ck77

Abstract: CK51 TADM04622
Contextual Info: Data Sheet, Revision 1 August 26, 2003 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer 1 Introduction The last issue of this data sheet was June 20, 2003. A revision history is included in 21 Revision History on page 65. Red change bars have been installed on all text, figures,

RXD55

Abstract: RXD26
Contextual Info: Hardware Design Guide June 2004 STSI-144 Scalable Time-Slot Interchanger Hardware Design Guide Introduction Related Documents This document describes the hardware interfaces to Agere Systems Inc. scalable time-slot interchanger STSI-144 device. Information relevant to the use of

Contextual Info: Preliminary Data Sheet May 2002 TSWC03622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch Features Description • Same functionality as TSWC01622 with reduced jitter specifications ■ Fully integrated clock synthesis ■ Clock or system sync protection switching

TSI-16

Abstract: TTSI144641BL-1 SI14 STSI-144
Contextual Info: Avance Information May 2002 STSI-144 Scalable Time-Slot Interchanger Product Description Introduction Features This document is a high-level description for the scalable time-slot interchanger STSI-144 device. The features and functions of the device are listed

Contextual Info: Avance Information August 2003 STSI-48 Scalable Time-Slot Interchanger Product Description Introduction Features This document is a high-level description for the scalable time-slot interchanger STSI-48 device. The features and functions of the device are listed

Contextual Info: Data Advisory October 25, 2002 TSWC01622/TSWC02622/TSWC03622/TSYN01622 Device Advisory for Version 1.1 of the Device Reference data sheets October 2002, TSWC01622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch data sheet DS02-237HSPL, TSWC02622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection

T400 clock

Abstract: TSWC01622 TSWC02622 TSWC03622 TSYN01622
Contextual Info: Data Advisory October 25, 2002 TSWC01622/TSWC02622/TSWC03622/TSYN01622 Device Advisory for Version 1.1 of the Device Reference data sheets October 2002, TSWC01622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch data sheet DS02-237HSPL, TSWC02622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection

TADM042G5

Abstract: TDAT042G5 TSOT0410G TSWC02622 TTRN012G5
Contextual Info: Preliminary Product Brief February 2003 TSWC02622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch Features Description • Fully integrated clock synthesis ■ Clock or system sync protection switching ■ Fast autonomous switching with software override

IR LFN detector

Abstract: LFN ir
Contextual Info: Advance Data Sheet September 1999 microelectronics group Lucent Technologies Bell Labs Innovations TRCV012G5 2.5 Gbits/s Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer Features Description • Fully integrated limiting amplifier, clock recovery,

dflj

Contextual Info: Advance Data Sheet September 1999 + microelectronics _ group Lucent Technologies m M Bell Labs Innovations TRCV012G5 2.5 Gbits/s Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer Features Description • Fully integrated limiting amplifier, clock recovery,

T400 clock

Abstract: ATM machine working circuit diagram TSWC01622 TSWC02622 TSWC03622 TSYN01622 TSYN03622 L2E4
Contextual Info: Advisory October 28, 2003 TSWC01622/TSWC02622/TSWC03622/TSYN01622/TSYN03622 Device Version 1.1 Advisory The following data sheets are to be referenced: • TSWC01622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch data sheet DS03-117HSPL-1 . ■

Contextual Info: * SONET OC-12/OC-3 CLOCK SYNTHESIZER SYNERGY SEMICONDUCTOR Clockworks SY89426 DESCRIPTION FEATURES • Single chip source for 622.08MHz and 155.52MHz clocks Synergy's SY89426 M ulti-O utput Phase Locked Loop PLL is a SONET com pliant clock generator providing

Contextual Info: * SONET OC-12/OC-3 CLOCK SYNTHESIZER SYNERGY SEMICONDUCTOR Clockworks SY89426 DESCRIPTION FEATURES • Single chip source for 622.08MHz and 155.52MHz clocks ■ 622.08MHz output is differential PECL, 155.52MHz output is single-ended PECL ■ TTL/CMOS compatible inputs and reference output

2ya18

Abstract: nortel demux ya18 FZT968 nortel YA YA19 YA20 AB89 AC10 OC48
Contextual Info: YA18 2.5 Gb/s Clock and Data Recovery Circuit Data Sheet Features Fully balanced, differential architecture from input to output Differential CML data input accepts signals of up to 2.7 Gb/s data rates - 50 Ω terminated 50 Ω terminated differential CML

optical external modulator

Abstract: CK311 NTD10 OC48 TD10 TQ8214 td10 1400 NTD13 TriQuint Optoelectronics
Contextual Info: R I Q U I N T S E M I C O N D U C T O R, I N C . The TQ8214 is a SONET/SDH OC48 MUX that time-division multiplexes a 16-bit or 8-bit parallel data bus to a serial 2.48832 Gb/s NRZ data stream for transmission through a communications channel. Without any additional amplification, the 2.48832 Gb/s output stage can drive either a

GR-253

Abstract: TRCV012G5 TTRN012G5
Contextual Info: Product Brief October 1999 TTRN012G5 2.5 GHz Clock Synthesizer, 16:1 Data Multiplexer Features • Fully integrated 2.5 GHz clock synthesizer; 16:1 data multiplexer; supports OC-48/STM-16 data rates ■ Supports clockless data transfer into the 16:1 multiplexer

GR-253

Abstract: TRCV012G5 TTRN012G5
Contextual Info: Product Brief August 1999 TRCV012G5 2.5 Gbits/s Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer Features • Fully integrated limiting amplifier, clock recovery, 1:16 data demultiplexer ■ Supports OC-48/STM-16 data rates, including 2.66 Gbits/s forward error correction FEC

K1555

Abstract: RQ48 CK311 CK38 TQ8223 D1294 RQ-15 resistor 40-1-88 RQ23 rq31
Contextual Info: T R I Q U I N T S E M I C O N D U C T O R, I N C . TQ8223 The TQ8223 is extremely flexible for telecom, ATM and networking applications. The serial 2.48832 Gb/s data stream is demultiplexed into a 32-bit wide 77.76 MHz TTL data bus. Internal data inversion is also