CK G Search Results

CK-04

Abstract: electrolytic capacitor 22/25 capacitor package CK-01 Non-polarized Radial Aluminum Electrolytic Capacitor CK-03
Contextual Info: PRE-PACKAGED CAPACITOR KITS CAPACITOR KITS CK-01 CK-02 CK-03 CK-04 -Aluminum Electrolytic -High Voltage Aluminum Electrolytic -Non-Polarized Aluminum Electrolytic -Tantalum CK-05 CK-06 CK-07 - 50V Ceramic Disc - 1000V Ceramic Disc - Mylar/Film Features: •

.01 uf disc capacitor

Abstract: capacitor 4700 uF 50V ELECTROLYTIC capacitor 2200 uF 50V .22 uf disc capacitor electrolytic capacitor 25 volts capacitor 0.47 uF 50V 20 ELECTROLYTIC capacitor 1200 uF capacitor CK-06 1000 uf 50v CK-04
Contextual Info: PRE-PACKAGED CAPACITOR KITS CAPACITOR KITS CK-01 CK-02 CK-03 CK-04 -Aluminum Electrolytic -High Voltage Aluminum Electrolytic -Non-Polarized Aluminum Electrolytic -Tantalum CK-05 CK-06 CK-07 - 50V Ceramic Disc - 1000V Ceramic Disc - Mylar/Film Features: •

74F420

Abstract: F420 D2939
Contextual Info: 420 54F/74F420 C o nn ectio n Diagram s Parallel Check Bit/Syndrome Bit Generator a lle i ch e ck bit/syndrom e bit generator. The ’ F420 ming code to generate 7 ch e ck bits from a 32-bit en operated in the ch e ck bit generate mode. When romjfffjjftosrate mode, the ch e ck bits and data bits

74374

Abstract: 74574 74534 ZD2020 74575
Contextual Info: - 246- 745 34 Octal 3-State D-FFs Inverted 7D c 7Q r f 5ff 6D 5D 55 S C p r r j l CK* - 1 — »CK OE ^ CK* — |p—4 *CK l £ J T ' I _CK* — <— *CK _ OUTPUT IQ CONTROL 10 , U 5 C P 2D '+ OE I r h _CK* — - * C K _ b 3 h I 4 CLOCK 25 3 i 30 40 i3 GN D

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dynam ic S w itch PLL C lock D river M PC993 The M PC 993 is a PLL c lo ck drive r de sign ed spe cifically for redundant clo ck tree designs. T h e d e vice rece ives tw o differential LVP EC L clo ck sig nals from w hich it ge ne rates 5 new differential LVP EC L c lo ck outputs.

oszillator

Abstract: ZEN xf 2 DES 4
Contextual Info: CK 3 CK 3 Oktode Die CK 3 ist eine Oktode nach dem Vierbündelprinzip. Sie ist bis auf die Heizdaten mit der Vierbündeloktode EK 3 für Wechselstromempfän­ ger identisch. Nur wurde wegen des 100-Volt-Betriebes das sechste Gitter etwas geändert. Die für die EK 3 gemachten Angaben gelten auch

84x4

Contextual Info: 256Mb sTSOPII DDR SDRAM Key Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe DQS • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition

Contextual Info: Preliminary DDR SDRAM 256Mb Key Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe DQS • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition

DDR200

Abstract: DDR266 DDR333 256mb ddr333 200 pin K4H560438D
Contextual Info: 256Mb sTSOPII DDR SDRAM Key Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe DQS • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition

K4H5

Abstract: K4H561638D 256mb ddr333 200 pin K4H561638D-TC
Contextual Info: 256Mb DDR SDRAM Key Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe DQS • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition

CL25

Contextual Info: 256Mb DDR SDRAM Key Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe DQS • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition

256mb ddr333 200 pin

Abstract: DDR266 DDR266A DDR266B DDR333 K4H560438D-GC K4H561638D
Contextual Info: 256Mb DDR SDRAM Key Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe DQS • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition

12v AC to DC CIRCUIT DIAGRAM

Contextual Info: 256Mb DDR SDRAM Key Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe DQS • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition

Contextual Info: MC14538BCP IL08D C-MOS DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORS —TOP VIEW— VDD 1-C 1 R C VDD 16 1 1-CR 2 Q 4 15 7 Q RD 13 2-RD 1-CK 5 12 2-CK 1-Q 6 11 2-CK 1-Q 7 10 2-Q 8 GND Q 12 10 11 Q 1-CK 4 14 6 5 14 2-CR R C 2 15 2-C 1-RD 3 VDD 9 RD 3 13 OUTPUT PULSE WIDTH = C . R

48MHZ

Abstract: CK-408 CY28324 SSOP-48 105839
Contextual Info: CY28324 PRELIMINARY FTG for Intel Pentium 4 CPU and Chipsets Features • Compatible to Intel CK-00, CK-Titan & CK-408 Clock Synthesizer/Driver Specifications • System frequency synthesizer for Intel Pentium® 4 clasee processor • Programmable clock output frequency with less than 1

DDR300

Abstract: PC2400 DDR333 NT5DS16M8AT NT5DS16M8AW NT5DS32M4AT PC2700
Contextual Info: NT5DS32M4AT NT5DS32M4AW NT5DS16M8AT NT5DS16M8AW 128Mb DDR333/300 SDRAM Features • DLL aligns DQ and DQS transitions with CK transitions, also aligns QFC transitions with CK during Read cycles • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS

socket FM2

Abstract: PZ90427-3126-01H
Contextual Info: o D E AS G EN E R A TE D D R A W IN G , D O N 'T CHANGE 3 BY 4 5 6 REV. HAND. 4 3 .0 8 ! _ A - a - j_ A SOCKE I D E T A IL A 77 FM2 A Cp£ LF a ^ D E T A IL APPD . BC-11-0034780 Di ck i e.H B BC-11-0107792 Di ck i e.H C BC-12-0010128 DI ck i e.H BC-12-0043322 Di ck i e.H

Contextual Info: W42C70-01 IL08 C-MOS FREQUENCY MULTIPLIER —TOP VIEW— 2 8 CK2 OUT FB IN 1 CK2 1 VDD 7 CK IN 2 4 3 GND FSEL0 IN 4 CK1 CK 6 CK1 OUT 5 6 8 FB FSEL0 FSEL1 5 FSEL1 IN FREQUENCY SELECTION FSEL1 FSEL0 FB FREQ. 2 • fIN 4 • fIN 1 fIN 1 8 • fIN 1 1 INPUT CK

Contextual Info: CAT59C11HK * IL08 C-MOS 1K-BIT 64x16 /128x8 BIT SERIAL EEPROM -TOP VIEW- CS IN 1 CK IN V DD(+5V) 8 2 DI IN 7 3 6 DO OUT 4 GND 5 3 RY/BY 4 DI DO CK RY/BY 2 CS 1 ORG IN 7 ORG 6 CK ;CLOCK INPUT ;CHIP SELECT INPUT CS DI ;SERIAL DATA INPUT DO ;SERIAL DATA OUTPUT

CK-408

Abstract: CY28322-2 CK-408 CK-Titan Clock Synthesizer G2021
Contextual Info: PRELIMINARY CY28322-2 133-MHz Spread Spectrum Clock Synthesizer with Differential CPU Outputs Features Benefits  • Compliant with Intel CK-Titan and CK-408 clock synthesizer/driver specifications Supports next generation Pentium processors using differential clock drivers

48MHZ

Abstract: CK-408 CY28324 SSOP-48 CK-408 CK-Titan Clock Synthesizer intel 845 circuit diagram
Contextual Info: CY28324 FTG for Intel Pentium® 4 CPU and Chipsets Features • Support SMBus byte read/write and block read/write operations to simplify system BIOS development • Compatible to Intel® CK-00, CK-Titan & CK-408 Clock Synthesizer/Driver Specifications • System frequency synthesizer for Intel 850, Brookdale

Contextual Info: w FSP TECHNOLOGY INC. PM HEF. ID. NO. /2 4 WIRE COLOR ORA N G E 4 RE D ORA N G E BLA CK 5 +5VDC COM 6 +5VDC RED 7 COM BLA CK B PW-OK +5V sb GRA Y PU RPLE 9 10 PI SIGNAL 1 +3.3VDC 2 +3.3VDC 3 COM BLA CK +12VDC Y ELLO W 11 +12VDC Y ELLO W 12 +3.3VDC 13 +3.3VDC

Contextual Info: M62354P 1/3 IL00D C-MOS 8-BITS 6 CHANNEL D/A CONVERTER —TOP VIEW— 4 DO OUT 1 VDD 14 13 V1 IN LD IN 2 CK IN 3 12 A06 OUT DI IN 4 11 A05 OUT A01 OUT 5 10 A04 OUT A02 OUT 6 9 A03 OUT 7 GND A01 - A06 CK DI DO LD V1 V2 ; ; ; ; ; ; ; 3 2 DI DO 1 CK LD A01

Contextual Info: MC74HC4538N IL00 C-MOS DUAL RETRIGGERABLE/NON-RETRIGGERABLE MONOSTABLE MULTIVIBRATOR —TOP VIEW— VDD 1-C 1 VDD 16 C R 1 1-CR 2 5 1-CK 4 13 2-RD 1-CK 5 12 2-CK 1-Q 6 11 2-CK 1-Q 7 10 2-Q 15 6 Q 4 14 2-CR C 2 15 2-C 1-RD 3 VDD 14 Q 10 12 11 Q 7 RD R Q 9 RD