CK 158 Search Results
CK 158 Price and Stock
Knowles CDE 158CKS010MAluminum Electrolytic Capacitors - Radial Leaded 1500uF 10V 20% tol ELECTROLYTIC |
|||||||||||
| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
|
158CKS010M | 7,804 |
|
Buy Now | |||||||
Texas Instruments SN74AUP1T158DCKRTranslation - Voltage Levels Low Pwr 1.8/2.5/3.3 Vin 3.3V CMOS Out |
|||||||||||
| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
|
SN74AUP1T158DCKR | 4,759 |
|
Buy Now | |||||||
Renesas Electronics Corporation R7F7015873AFP-C#AA332-bit Microcontrollers - MCU 32BIT MCU RH850/F1K-PREMIUM |
|||||||||||
| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
|
R7F7015873AFP-C#AA3 | 3,871 |
|
Buy Now | |||||||
LEDIL F15859_HEKLA-SOCKET-ILED Lighting Accessories & Hardware Round Base Part 1 Position |
|||||||||||
| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
|
F15859_HEKLA-SOCKET-I | 798 |
|
Buy Now | |||||||
Renesas Electronics Corporation R7F7015813AFP-C#AA332-bit Microcontrollers - MCU 32BIT MCU RH850/F1K 100PIN 2MB 105C |
|||||||||||
| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
|
R7F7015813AFP-C#AA3 | 326 |
|
Buy Now | |||||||
CK 158 Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
|---|---|---|---|
DDR200
Abstract: DDR266 DDR333 W3EG6433S-AD4
|
Original |
w3eg6433s-ad4256mb32mx64ddr200+4 | |
|
Contextual Info: White Electronic Designs WED3EG6465S-D3 64MB- 8Mx64 SDRAM UNBUFFERED FEATURES Double-date-rate architecture Bi-directional data strobes DQS Differential clock inputs (CK CK) Programmable Read Latency 2, 2.5 (clock) Programmable Burst Length (2,4,8) |
Original |
wed3eg6465s-d38mx64wed3edg6465s64mx64+6 | |
|
Contextual Info: White Electronic Designs W3EG7235S-JD3 PRELIMINARY* 256MB - 32Mx72 DDR SDRAM REGISTERED ECC, w/PLL FEATURES Double-data-rate architecture Speeds of 100MHz and 133MHz Bi-directional data strobes DQS Differential clock inputs (CK# & CK) |
Original |
w3eg7235s-jd3256mb32mx72100mhz+4 | |
|
Contextual Info: White Electronic Designs W3EG72125S-D3 -JD3 -AJD3 PRELIMINARY 1GB - 128Mx72 DDR SDRAM REGISTERED ECC w/PLL FEATURES DESCRIPTION Double-data-rate architecture Clock Speeds of 100MHz, 133MHz and 166MHz Bi-directional data strobes DQS Differential clock inputs (CK & CK#) |
Original |
w3eg72125s-d3128mx72100mhz133mhz+4 | |
|
Contextual Info: White Electronic Designs WED3EG648S-D4 64MB- 8Mx64 DDR SDRAM UNBUFFERED FEATURES Double-data-rate architecture Bi-directional data strobes DQS Differential clock inputs (CK & CK#) Programmable Read Latency (2,4,8) Programmable Burst type (sequential & interleave) |
Original |
8mx64wed3eg648s-d4wed3dg648s128mb+5 | |
DDR200
Abstract: DDR266 DDR333 W3EG72125S-D3
|
Original |
w3eg72125s-d32x64mx72100mhz133mhz+7 | |
|
Contextual Info: White Electronic Designs WED3EG64129S-D3 *ADVANCED 1G- 128Mx64 DDR SDRAM UNBUFFERED FEATURES n Double-data-rate architecture n Bi-directional data strobes DQS n Differential clock inputs (CK & CK#) n Programmable Read Latency 2,2,5 (clock) n Programmable Burst Length (2,4,8) |
Original |
128mx64wed3eg64129s-d3wed3dg64129s124mx64+5 | |
|
Contextual Info: White Electronic Designs WED3EG6437S-D4 *ADVANCED 256MB- 32Mx64 DDR SDRAM UNBUFFERED FEATURES n Double-data-rate architecture n Bi-directional data strobes DQS n Differential clock inputs (CK & CK#) n Programmable Read Latency 2,2,5 (clock) n Programmable Burst Length (2,4,8) |
Original |
wed3eg6437s-d4256mb-32mx64wed3dg6437s+5 | |
|
Contextual Info: White Electronic Designs WED3EG7232S-D3 *ADVANCED 256MB- 32Mx72 DDR SDRAM UNBUFFERED FEATURES Double-data-rate architecture Bi-directional data strobes DQS Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) |
Original |
256mb-32mx72wed3eg7232s-d3wed3dg7232s+5 | |
|
Contextual Info: White Electronic Designs WED3EG7233S-D3 *ADVANCED 256MB- 32Mx72 DDR SDRAM UNBUFFERED FEATURES Double-data-rate architecture Bi-directional data strobes DQS Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) |
Original |
256mb-32mx72wed3eg7233s-d3wed3dg7233s+5 | |
DDR200
Abstract: DDR266 DDR333 W3EG64128S-AD4
|
Original |
w3eg64128s-ad42x64mx64w3eg64128s512mb+4 | |
|
Contextual Info: White Electronic Designs WED3EG6418S-D3 *ADVANCED 128MB- 16Mx64 DDR SDRAM UNBUFFERED FEATURES n Double-data-rate architecture n Bi-directional data strobes DQS n Differential clock inputs (CK & CK#) n Programmable Read Latency 2,2,5 (clock) n Programmable Burst Length (2,4,8) |
Original |
wed3eg6418s-d3128mb-16mx64wed3eg6418s262d3+4 | |
|
Contextual Info: White Electronic Designs WED3EG72129S-D3 *ADVANCED 1GB- 128Mx72 DDR SDRAM REGISTERED FEATURES n Double-data-rate architecture n Bi-directional data strobes DQS n Differential clock inputs (CK & CK#) n Programmable Read Latency 2,2,5 (clock) n Programmable Burst Length (2,4,8) |
Original |
128mx72wed3eg72129s-d3wed3dg72129s512mb+5 | |
VCC166Contextual Info: White Electronic Designs WED3EG72128S-D3 1GB- 128Mx72 DDR SDRAM UNBUFFERED FEATURES Double-data rate architecture Speeds of 100MHZ, 133MHZ, 166MHZ BI-directional data strobes DQS Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) |
Original |
128mx72100mhz133mhz166mhz+7 | |
|
|
|||
samsung 5230
Abstract: DDR200 DDR266 DDR333 W3EG72125S-D3
|
Original |
w3eg72125s-d32x64mx72100mhz133mhz+8 | |
|
Contextual Info: White Electronic Designs WED3EG6434S-D3 *ADVANCED 256MB- 32Mx64 DDR SDRAM UNBUFFERED FEATURES n Double-data-rate architecture n Bi-directional data strobes DQS n Differential clock inputs (CK & CK#) n Programmable Read Latency 2,2.5 (clock) n Programmable Burst Length (2,4,8) |
Original |
wed3eg6434s-d3256mb-32mx64wed3eg6434s262d3+4 | |
|
Contextual Info: White Electronic Designs WED3EG7262S-D3 *ADVANCED 512MB- 64Mx72 DDR SDRAM UNBUFFERED FEATURES Double-data-rate architecture Bi-directional data strobes DQS Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) |
Original |
512mb-64mx72wed3eg7262s-d3wed3dg7262s+5 | |
|
Contextual Info: White Electronic Designs WED3EG7236S-D3 *ADVANCED 256MB- 32Mx72 DDR SDRAM REGISTERED FEATURES n Double-data-rate architecture n Bi-directional data strobes DQS n Differential clock inputs (CK & CK#) n Programmable Read Latency 2,2,5 (clock) n Programmable Burst Length (2,4,8) |
Original |
256mb-32mx72wed3eg7236s-d3wed3dg7236s+5 | |
|
Contextual Info: White Electronic Designs WED3EG6433S-D3 *ADVANCED 256MB- 32Mx64 DDR SDRAM UNBUFFERED FEATURES n Double-data-rate architecture n Bi-directional data strobes DQS n Differential clock inputs (CK & CK#) n Programmable Read Latency 2,2.5 (clock) n Programmable Burst Length (2,4,8) |
Original |
wed3eg6433s-d3256mb-32mx64wed3eg6433s262d3+4 | |
|
Contextual Info: White Electronic Designs W3EG7232S-AD4 -BD4 PRELIMINARY* 256MB- 32Mx72 DDR SDRAM UNBUFFERED w/PLL FEATURES DESCRIPTION n Double-data-rate architecture n Clock speeds of 100MHz and 133MHz n Bi-directional data strobes DQS n Differential clock inputs (CK & CK#) |
Original |
w3eg7232s-ad4256mb-32mx72100mhz+3 | |
a8152
Abstract: WED3EG6417S-D4
|
Original |
wed3eg6417s-d4128mb16mx64wed3dg6417s+4 | |
|
Contextual Info: W3EG6432S-D4 -AD4 -BD4 White Electronic Designs PRELIMINARY* 256MB - 32Mx64 DDR SDRAM UNBUFFERED FEATURES DESCRIPTION n Double-data-rate architecture n Industrial temperature n Bi-directional data strobes DQS n Differential clock inputs (CK & CK#) n Programmable Read Latency 2,2.5 (clock) |
Original |
256mb32mx64w3eg6432s-d4w3eg6432s | |
nanyaContextual Info: White Electronic Designs WV3EG232M64STSU-D4 PRELIMINARY* 512MB – 2x32Mx64 DDR SDRAM SO-DIMM UNBUFFERED FEATURES DESCRIPTION Fast Data Transfer Rate: PC2700 and PC3200 Double-data-rate architecture Bi-directional data strobes DQS Differential clock inputs (CK & CK#) |
Original |
wv3eg232m64stsu-d4512mb2x32mx64pc2700+5 | |
|
Contextual Info: White Electronic Designs WED3EG7218S-D3 *ADVANCED 128MB- 16Mx72 DDR SDRAM UNBUFFERED FEATURES Double-data-rate architecture BI-directional data strobes DQS Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) |
Original |
wed3eg7218s-d3128mb-16mx72wed3dg7218s+4 | |