BOUNDARY Search Results

74ABTH18646A

Contextual Info: SN54ABTH18646A, SN54ABTH182646A, SN74ABTH18646A, SN74ABTH182646A SCAN TEST DEVICES WITH 18-BIT TRANSCEIVERS AND REGISTERS SCBS166D - AUGUST 1993 - REVISED JULY 1996 Members of the Texas Instruments SCOPE Family of Testability Products One Boundary-Scan Cell Per I/O

LH75401

Abstract: LH75401N0Q100C0 LH75411 LH75411N0Q100C0 LQFP144
Contextual Info: LH75401/LH75411 System-on-Chip Preliminary data sheet DESCRIPTION • JTAG Debug Interface and Boundary Scan The NXP BlueStreak LH75401/LH75411 family consists of two low-cost 16/32-bit System-on-Chip SoC devices. • Single 3.3 V Supply • LH75401 — contains the superset of features.

10D-11

Abstract: K7R160982B K7R160982B-FC16 K7R160982B-FC20 K7R161882B K7R161882B-FC16 K7R161882B-FC20 K7R163682B K7R163682B-FC16 K7R163682B-FC20
Contextual Info: K7R163682B K7R161882B K7R160982B 512Kx36 & 1Mx18 & 2Mx9 QDR TM II b2 SRAM Document Title 512Kx36-bit, 1Mx18-bit, 2Mx9-bit QDRTM II b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. Oct. 17, 2002 Advance 0.1 1. Change the Boundary scan exit order.

t10-25 u2

Abstract: G2156 f10107
Contextual Info: Preliminary GS816273AC-300/275/250/225/200 300 MHz–200 MHz 256K x 72 1.8 V or 2.5 V VDD 18Mb S/DCD Sync Burst SRAMs 1.8 V or 2.5 V I/O 209-Pin BGA Commercial Temp Industrial Temp Features • Single/Dual Cycle Deselect selectable • IEEE 1149.1 JTAG-compatible Boundary Scan

SS45

Abstract: SC45F
Contextual Info: Ceramic Capacitors SS45 TYPE [SEMICONDUCTIVE BOUNDARY LAYER TYPE, 16, 25Vdc] SC45 TYPE [SEMICONDUCTIVE SURFACE LAYER TYPE, 25, 50Vdcl CLASS III n FEATURES * SS45 type • Semiconductive capacitors which consist of the insulation layer formed in the crystal particle field of

497AA

Abstract: lucent 497aa 7495 8-bit shift register 56308 programmable timer counter
Contextual Info: Product Brief July 1998 Lucent Boundary-Scan Master 497AA Introduction The Lucent Boundary-Scan Master BSM , the 497AA, communicates with a generic processor in parallel and controls the test/diagnosis (T&D) of a unit under test (UUT), which could be a device,

act8990

Abstract: SN54ACT8990 SN74ACT8990 sn74act8890
Contextual Info: SN54ACT8990, SN74ACT8990 TEST BUS CONTROLLERS SC AS190B - JUN E 1990 - REVISED A UG UST 1994 • Members of the Texas Instruments SCOPE Family of Testability Products * Compatible With the IEEE Standard 1149.1-1990 JTAG Test Access Port and Boundary-Scan Architecture

Actel A1225

Abstract: PL84 A1240XL actel a1240 A32140 PQ100C Cadence TQ176 PG176
Contextual Info: ^ c te l - w Integrator Series FPGAs: 1200XL and 3200DX Famüies Features a 4 L. ¡§ Cadence, Escalade, Exemplar, 1ST, Mentor Graphics, Synopsvs, and Viewlogic. High C a p a c ity • IEEE Standard 1149.1 JTAG Boundary Scan Testing.

HVR-1X 7 diode

Abstract: HV9805 HVR-1X 2 diode HVR-1X 6 diode
Contextual Info: Supertex inc. HV9805 High Voltage LED Driver General Description The HV9805 driver IC is targeted at driving high voltage LED strings from mains. High voltage LED strings offer an inherent cost advantage with respect to cooling and optics. A boundary mode boost

FAN6961

Abstract: BA 683 zvs flyback driver FAN6961DZ FAN6961SZ JESD22-A114 JESD22-A115 MS-001 VAC-265
Contextual Info: FAN6961 Boundary Mode PFC Controller Features Description ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ The FAN6961 is an 8-pin, boundary-mode, PFC controller IC intended for controlling PFC preregulators. The FAN6961 provides a controlled on-time to regulate the output DC voltage and achieve natural

Contextual Info: Introduction This manual provides the information needed to configure the PSX Family devices using the JTAG interface. It is intended for users who plan to write their own code to configure the PSX devices. In addition, this manual explains how the boundary scan features implemented in the PSX devices can be used

Contextual Info: JTAG Boundary-Scan Testing in Stratix V Devices 10 2013.05.06 SV51012 Subscribe Feedback This chapter describes the boundary-scan test BST features in Stratix V devices. Related Information Stratix V Device Handbook: Known Issues Lists the planned updates to the Stratix V Device Handbook chapters.

Contextual Info: Java Boundary-Scan API: Enabling Technology for Internet–Driven PLD Systems Background When first introduced, programmable logic devices were used primarily to facilitate rapid prototyping and debug of systems under development. As the price of programmable devices fell, their use increased

ABT245

Abstract: F244 F245 SN74ABT8245 SN74ABT8952 SN74ABT8952DW SN74BCT8244A an7005 ti8245
Contextual Info: Using ispGDX to Replace Texas Instruments Boundary Scan Bus Devices TM sible, especially with 5.0 ns Tpd and Tco. After a brief overview of the ispGDX architecture, several examples illustrating the use of the ispGDX devices for boundary scan bus devices follow. For more detailed information

Contextual Info: User Manual October 1998 group Lucent Technologies Bell Labs Innovations 497AE and 1215E Boundary-Scan Master 2 Advanced Operational Mode Features • The BSM2 is available in 2 versions: — The 497AE is available in a 28-pin SOJ pack­ age. — The 1215E device is available in a 48-pin TQFP

CRC-32

Abstract: PM5357 rfpo
Contextual Info: PM5357 S/UNI-622-POS PMC-Sierra,Inc. 622 Mbit/s ATM and Packet Over SONET Physical Layer Device FEATURES microprocessor interface for device control and register access • Provides standard IEEE 1149.1 JTAG test port for boundary scan GENERAL • ATM and Packet over SONET/SDH

Contextual Info: 8 File No. 1.60 Boundary Of Conn. Tær F I il qi O rientation Thru Hole * ^ ? I ISHEET 1 / SPECIFICATIONS Housing:PA 6T 15%G.F ,UL 9 4 V -0 Contact:C521 OR—H Shell:Brass Voltage:30V Current 1.5A COntact Resistance:50 Milliohms Max. Shell Resistance: 100Megohms Min.

Contextual Info: PRELIMINARY CY37192V UltraLogic 3.3V 192-Macrocell ISR™ CPLD — tPD = 12 ns Features — ts = 7 n s • 192 macrocells in twelve logic blocks • IEEE standard 3.3V operation — tco = 6.5 ns Product-term clocking IEEE 1149.1 JTAG boundary scan Programmable slew rate control on individual l/Os

Contextual Info: 1 8 I File No. 400 I SHEET o 1 ~ / SPECIFICATIONS Boundary Of Conn. Orientation Thru Hole HousingrPA 6T 15%G.F ,UL 9 4 V - 0 Contact:C521 OR— H Shell:Brass Voltage:30V Current 1.5A COntact Resistance:50 Milliohms Max. Shell Resistance: 100M egohm s Min.

CMZ5934B

Abstract: 750311564
Contextual Info: LT8302 42VIN Micropower No-Opto Isolated Flyback Converter with 65V/3.6A Switch Features Description 2.8V to 42V Input Voltage Range n 3.6A, 65V Internal DMOS Power Switch n Low Quiescent Current: 106µA in Sleep Mode 380µA in Active Mode n Quasi-Resonant Boundary Mode Operation at

CRC-32

Abstract: PM5357 TERR
Contextual Info: PM5357 S/UNI-622-POS PMC-Sierra,Inc. 622 Mbit/s ATM and Packet Over SONET Physical Layer Device FEATURES microprocessor interface for device control and register access • Provides standard IEEE 1149.1 JTAG test port for boundary scan GENERAL • ATM and Packet over SONET/SDH

Contextual Info: ispLSI 3256 High Density Programmable Logic Functional Block Diagram A1 OR Array A2 A3 B1 B2 B3 N C0 C1 C2 R D Q F1 Twin GLB F0 D Q E3 D Q E2 D Q E1 Global Routing Pool E0 C3 Output Routing Pool • 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE F2 D Q Array

5962-96B02

Abstract: fpga radiation 80C31 "UNITED TECHNOLOGIES MICROELECTRONICS"
Contextual Info: Semicustom Products UTE/UTE-R Gate Array Family Data Sheet May 1996 FEATURES Up to 125,000 usable equivalent gates QML Q and V compliant Designed specifically for high reliability applications Advanced sub-micron 0.9 leff silicon gate CMOS process JTAG (IEEE 1149.1) boundary-scan registers built into I/O

D-xxxV

Abstract: GS88237BB-200 GS88237BB-200V GS88237BB-250IV GS88237BB-250V
Contextual Info: GS88237BB/D-xxxV 119- & 165-Bump BGA Commercial Temp Industrial Temp 256K x 36 9Mb SCD/DCD Sync Burst SRAM Features • Single/Dual Cycle Deselect selectable • IEEE 1149.1 JTAG-compatible Boundary Scan • ZQ mode pin for user-selectable high/low output drive