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    Maxim Integrated Products MAX17497AATE+T

    AC/DC and DC/DC Peak Current Mode Converter 16-Pin TQFN EP T/R
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    Bristol Electronics MAX17497AATE+T 2,500 1
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    • 100 $10.69
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    Bristol Electronics 497AA 15
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    Alcatel-Lucent 497AA

    BOUNDARY-SCAN MASTER (BSM)
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    Quest Components 497AA 72
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    Axiom Manufacturing JD497A-AX

    Axiom SFP Module
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    Neutron USA JD497A-AX
    • 1 $139.99
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    Vyrian MAX17497AATE-T 11,625
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    497AA Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    497AA

    Abstract: lucent 497aa 7495 8-bit shift register 56308 programmable timer counter
    Contextual Info: Product Brief July 1998 Lucent Boundary-Scan Master 497AA Introduction The Lucent Boundary-Scan Master BSM , the 497AA, communicates with a generic processor in parallel and controls the test/diagnosis (T&D) of a unit under test (UUT), which could be a device,


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    497aapn98-167ntnbpn92-008bsmlucent 497aa+37495 8-bit shift register56308programmable timer counter PDF

    Contextual Info: AT&T Product Specification Sheet Microelectronics 497AA Initial Use BSM 5E S S Description The 497AA BSM is a 28-pin, 1.25 pm CMOS IC with TTL compatible inputs and outputs. The BSM interfaces the serial JTAG/IEE Standard 1149.1 Test Access Port TAP with the parallel bus of either a


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    497aa28-pin PDF

    00XXX001

    Abstract: BA 5979 R15C3 OR3T125 OR3T20 OR3T30 OR3T55 PT10 PT11 PT12
    Contextual Info: Data Sheet November 2006 ORCA Series 3C and 3T Field-Programmable Gate Arrays Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Baseline FPGA family used in Series 3+ FPSCs field programmable system chips which combine FPGA logic


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    or3t20or3t301a-06or3t80+800xxx001ba 5979r15c3or3t125or3t55pt10pt11pt12 PDF

    Contextual Info: User Manual October 1998 group Lucent Technologies Bell Labs Innovations 497AE and 1215E Boundary-Scan Master 2 Advanced Operational Mode Features • The BSM2 is available in 2 versions: — The 497AE is available in a 28-pin SOJ pack­ age. — The 1215E device is available in a 48-pin TQFP


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    497ae1215e28-pin48-pin PDF

    Contextual Info: AT&T Data Sheet October 1995 Microelectronics Optimized Reconfigurable Cell Array ORCA 2C Series Field-Programmable Gate Arrays Features Description • High-performance, cost-effective 0.5 |im technology (four-input look-up table delay less than 3.6 ns)


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    att2c04att2c06att2c08att2c10+6att2c12att2c15att2c26att2c40ds95-183fpgads95-031 PDF

    Contextual Info: User Manual September 1998 group Lucent Technologies Bell Labs Innovations 497AE and 1215E Boundary-Scan Master 2 Advanced Operational Mode F e a tu re s • The BSM2 is available in 2 versions: — The 497AE is available in a 28-pin SOJ pack­ age. — The 1215E device is available in a 48-pin TQFP


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    497ae1215e28-pin48-pin PDF

    IC TTL 7495 diagram and truth table

    Abstract: BA 5979 S AM 5766 BA 5979 motorola s240 pin diagram of ic 7495 Xilinx counter transistor on 4409 PR25D inverter design using plc
    Contextual Info: Data Sheet June 1999 ORCA Series 3C and 3T Field-Programmable Gate Arrays Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance, cost-effective, 0.35 µm OR3C and 0.3 µm (OR3T) 4-level metal technology, (4- or 5-input look-up table delay of 1.1 ns with -7 speed grade in


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    ds99-087fpgads98-163fpga-01ic ttl 7495 diagram and truth tableba 5979 s+8am 5766ba 5979motorola s240pin diagram of ic 7495xilinx countertransistor on 4409pr25dinverter design using plc PDF

    transistor pt36c

    Abstract: datasheet transistor pt36C PT35c transistor pt36c microprocessor block diagram of plc pt35c transistor pt42c PT42C transistor BC 157 PLC Communication cables pin diagram
    Contextual Info: Data Sheet November, 2003 ORCA Series 4 FPGAs Introduction • Traditional I/O selections: — LVTTL 3.3V and LVCMOS (2.5 V and 1.8 V) I/Os. — Per pin-selectable I/O clamping diodes provide 3.3 V PCI compliance. — Individually programmable drive capability:


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    sink/12transistor pt36cdatasheet transistor pt36cpt35c transistor+7pt36cmicroprocessor block diagram of plcpt35ctransistor pt42cpt42ctransistor bc 157plc communication cables pin diagram PDF

    BA 5979 S

    Abstract: or3t806ba352-db 2764 EEPROM BA 5979 BL06 transistor OR3T125 OR3T20 OR3T30 OR3T55 PT10
    Contextual Info: Data Sheet November 2006 ORCA Series 3C and 3T Field-Programmable Gate Arrays Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance, cost-effective, 0.35 m OR3C and 0.3 μm (OR3T) 4-level metal technology, (4- or 5-input look-up table delay of 1.1 ns with -7 speed grade in


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    or3c804ps208i-dbor3c804ba352i-dbor3t206s208i-dbor3t306s208i-db+16or3t306s240i-dbor3t306ba256i-dbor3t556ps208i-db1or3t556s208i-dbor3t556ps240i-dbor3t556ba256i-dbba 5979 sor3t806ba352-db2764 eepromba 5979bl06 transistoror3t125or3t20or3t30or3t55pt10 PDF

    1C07

    Abstract: plj1 ATT ORCA fpga architecture ATT ORCA fpga HC s304 1C09 ic all pics IC PIN CONFIGURATION OF 74 47 1C03 1C05
    Contextual Info: AT&T Data Sheet March 1995 ' Microelectronics Optimized Reconfigurable Cell Array {ORCA 1C Series Field-Programmable Gate Arrays ATT1C03, ATT1C05, ATT1C07, and ATT1C09) Features • High density: to 11,400 usable gates ■ High I/O: up to 256 usable I/O (forATT1C09)


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    att1c03att1c05att1c07att1c09+16foratt1c0916-bit84-pin100-pin132-pin144-pin1c07plj1att orca fpga architectureatt orca fpgahc s3041c09ic all picsic pin configuration of 74 471c031c05 PDF

    PT15D

    Abstract: OR2T40A-6PS208I R4C18
    Contextual Info: Data Sheet August 2002 ORCA Series 2 Field-Programmable Gate Arrays Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance, cost-effective, low-power 0.35 µm CMOS technology OR2CxxA , 0.3 µm CMOS technology (OR2TxxA), and 0.25 µm CMOS technology


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    16-bit32-bitor2t10aor2t15a+9or2t15bor2t26aor2t40aor2t40bds99-094fpgads98-022fpgapt15dor2t40a-6ps208ir4c18 PDF

    BA 5979

    Abstract: br06 lm 398- SAMPLE AND HOLD OR3T125 OR3T20 OR3T30 OR3T55 PT10 diagram for 3 bits binary multiplier circuit ic 7490 truth table
    Contextual Info: Data Sheet March 2002 ORCA Series 3C and 3T Field-Programmable Gate Arrays Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance, cost-effective, 0.35 µm OR3C and 0.3 µm (OR3T) 4-level metal technology, (4- or 5-input look-up table delay of 1.1 ns with -7 speed grade in


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    ba 5979br06lm 398- sample and holdor3t125+6or3t20or3t30or3t55pt10diagram for 3 bits binary multiplier circuitic 7490 truth table PDF

    lucent 497aa

    Abstract: PT12B PT18C PT15D la 4508 ic schematic diagram pt8c PR12D pr19a ATT2C26 sj 2206 b
    Contextual Info: Lucent Technologies Bell Labs Innovations Optimized Reconfigurable Cell Array ORCA ATT2Cxx Series Field-Programmable Gate Arrays Features Description • High-performance, cost-effective 0.5 urn technology (four-input look-up table delay less than 3.6 ns)


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    144-pin160-pin256-p364-p+16428-patt2c04att2c06att2c08att2c10att2c12lucent 497aapt12bpt18cpt15dla 4508 ic schematic diagrampt8cpr12dpr19aatt2c26sj 2206 b PDF

    tic 2250

    Abstract: 2c14r ap13 eam
    Contextual Info: Preliminary Data Sheet May 1998 m icroelectronics group Lucent Technologies Bell Labs Innovations ORCA 0R3Cxx 5 V and 0R3Txxx (3.3 V) Series Field-Programmable Gate Arrays Features • High-performance, cost-effective, 0.35 4-level metal technology, with a migration plan to 0.25


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    16-bittwo58ds98-163fpgads97-282fpga+3tic 22502c14rap13 eam PDF

    ATT ORCA fpga

    Abstract: ATT ORCA fpga architecture
    Contextual Info: Data Sheet May 1995 f^ A D s T Microelectronics Optimized Reconfigurable Cell Array {ORCA 1C Series Field-Programmable Gate Arrays ATT1C03, ATT1C05, ATT1C07, and ATT1C09) Features • High density: to 11,400 usable gates ■ High I/O: up to 256 usable I/O (for ATT1C09)


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    att1c03att1c05att1c07att1c09+516-bitds95-084fpgads94-131fpgaatt orca fpgaatt orca fpga architecture PDF

    BA 5979 S

    Abstract: how many pins in IC 4538 BA 5979 24 micro farad capacitor datasheet 3T80 transistor on 4409 AM 5766 ba 5412 PR25D or3t806ba352-db
    Contextual Info: Data Sheet December 2002 ORCA Series 3C and 3T Field-Programmable Gate Arrays Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance, cost-effective, 0.35 µm OR3C and 0.3 µm (OR3T) 4-level metal technology, (4- or 5-input look-up table delay of 1.1 ns with -7 speed grade in


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    or3t806ba352i-dbor3t806bc432i-dbor3t1256ps208i-dbor3t1256ps240i-db+13or3t1256ba352i-dbor3t1256bc432i-dbor3t1256bc600i-dbba 5979 show many pins in ic 4538ba 597924 micro farad capacitor datasheet3t80transistor on 4409am 5766ba 5412pr25dor3t806ba352-db PDF

    Contextual Info: Data Sheet June 1999 microelectronics group Lucent Technologies Bell Labs Innovations ORCA Series 3C and 3T Field-Programmable Gate Arrays Features • High-performance, cost-effective, 0.35 pm OR3C and 0.3 pm (OR3T) 4-level metal technology, (4- or 5-input


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    gd3t75fci PDF

    Contextual Info: Datasheet microelectronics group June 1999 Lucent Technologies Bell Labs Innovations ORCA Series 2 Field-Programmable Gate Arrays Features • High-performance, cost-effective, low-power 0.35 pm CMOS technology OR2CxxA , 0.3 pm CMOS technology (OR2TxxA), and 0.25 pm CMOS technology


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    16-bit PDF

    Contextual Info: Data Sheet August 1996 microelectronics group Lucent Technologies Bell Labs Innovations ORCA OR2CxxA 5.0 V and OR2TxxA (3.3 V) Series Field-Programmable Gate Arrays Features • Flip-flop/latch options to allow programmable prior­ ity of synchronous set/reset vs. clock enable


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    ds96-140fpgds96-025fpgaqqs110b PDF

    PT43C

    Abstract: PR41C pin diagram of ic 7495 shift register CORE F5A Y 928 K00 064 PT42C 21-INPUT pr46c OR4E10 k72 u2
    Contextual Info: Preliminary Data Sheet August 2000 ORCA Series 4 Field-Programmable Gate Arrays Programmable Features • ■ High-performance platform design. — 0.13 µm seven-level metal technology. — Internal performance of >250 MHz four logic levels . — I/O performance of >416 MHz for all user I/Os.


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    ds00-221fpgapt43cpr41cpin diagram of ic 7495 shift register+7core f5ay 928 k00 064pt42c21-inputpr46cor4e10k72 u2 PDF

    EXO 32K

    Abstract: OR2C06A OR2C12A OR2T15B OR2T40B
    Contextual Info: Data Sheet November 2006 ORCA Series 2 Field-Programmable Gate Arrays Features • ■ ■ ■ ■ ■ ■ ■ ■ High-performance, cost-effective, low-power 0.35 µm CMOS technology OR2CxxA , 0.3 µm CMOS technology (OR2TxxA), and 0.25 µm CMOS technology


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    16-bit32-bitds99-094fpgads98-022fpga+5exo 32kor2c06aor2c12aor2t15bor2t40b PDF

    R14C17

    Abstract: R16C17
    Contextual Info: September 1995 j-s #*•«*■ Microelectronics Optimized Reconfigurable Cell Array ORCA ATT2T15 (3.3 V) Field-Programmable Gate Array Features Description ■ High-performance, cost-effective 0.5 jam technology optimized for 3.3 V operation The ATT2T15 is the first device in this family opti­


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    att2t15att2c15005002br14c17+1r16c17 PDF

    PT15D

    Abstract: 8C14 M31 mkv decoder chip diagram D172C ptoc5 Lucent 2623
    Contextual Info: Data Sheet January 1998 microelectronics group Lucent Technologies Bell Labs Innovations ORCA OR2CXXA 5.0 V and OR2TxxA (3.3 V) Series Field-Programmable Gate Arrays Features • High-performance, cost-effective, low-power 0.35 |xm/0.3 |xm CMOS technology, with a migration


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    16-bitds98-022fpgads96-140fpgada97-006fpga+7da97-012fpgapt15d8c14 m31mkv decoder chip diagramd172cptoc5lucent 2623 PDF

    CORE F5A

    Contextual Info: Preliminary Data Sheet August 2000 m i c r o e le c t r o n ic s group Lucent Technologies Bell Labs Innovations ORCA Series 4 Field-Programmable Gate Arrays Programmable Features • High-performance platform design. — 0.13 pm seven-level metal technology.


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    ds00-221fpgacore f5a PDF