BE3L Search Results

A12L

Abstract: A14L IDT70V3579 IDT70V3579S
Contextual Info: HIGH-SPEED 3.3V 32K x 36 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM Features: ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: 5/6ns max. Pipelined output mode

70V3569

Abstract: A12L A13L IDT70V3569 IDT70V3569S
Contextual Info: HIGH-SPEED 3.3V 16K x 36 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE PRELIMINARY IDT70V3569S Features: ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed clock to data access

tdc 310

Abstract: ba6l BA6R 10 35L U1
Contextual Info: HIGH-SPEED 3.3V 256K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ 256K x 36 Synchronous Bank-Switchable Dual-ported SRAM Architecture – 64 independent 4K x 36 banks – 9 megabits of memory on chip

be5l

Abstract: CA3046 equivalent lg 15.6 pinout CA3046 CA3046M BE4L d143 T transistor
Contextual Info: CA3045' CA3046 H A R R 'S M S E M I C O N D U C T O R J M • W » W General Purpose NPN Transistor Arrays N o vem b er 1996 Features Description • Two Matched Transistors T he C A 3 04 5 and C A 3 04 6 each co n sist o f five general p u rpo se silicon NPN transisto rs on a com m on m on olithic

Contextual Info: FUJITSU SEMICONDUCTOR DATA SHEET DS04-22420-1E ASSP Communication Control CMOS Wide Fast-20 SCSI Protocol Controller With PCI Interface MB86606 • DESCRIPTION The MB86606 is an intelligent SCSI Protocol Controller SPC which com plies with ANSI (FAST-20) standard

ba6l

Contextual Info: HIGH-SPEED 3.3V 64K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ 64K x 36 Synchronous Bank-Switchable Dual-ported SRAM Architecture – 64 independent 1K x 36 banks – 2 megabits of memory on chip

CYD01S36V

Abstract: CYD02S36V CYD04S36V CYD09S36V CYD18S36V 1.0mm pitch BGA
Contextual Info: CYD01S36V CYD02S36V/CYD04S36V CYD09S36V/CYD18S36V PRELIMINARY FLEx36TM 3.3V 32K/64K/128K/256K/512 x 36 Synchronous Dual-Port RAM Features Functional Description • True dual-ported memory cells that allow simultaneous access of the same memory location The FLEx36 family includes 1-Mbit, 2-Mbit, 4-Mbit, 9-Mbit and

IDT70T659

Contextual Info: HIGH-SPEED 2.5V 256/128K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE Features ◆ ◆ ◆ ◆ ◆ ◆ Busy and Interrupt Flags On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port

10 35L U4

Abstract: 70V7589 IDT70V7589 IDT70V7589S BA5L
Contextual Info: HIGH-SPEED 3.3V 64K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE PRELIMINARY IDT70V7589S Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ 64K x 36 Synchronous Bank-Switchable Dual-ported SRAM Architecture – 64 independent 1K x 36 banks

IDT70T659

Abstract: 9S12 CAN 9S12
Contextual Info: Š Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ IDT70T651/9S HIGH-SPEED 2.5V 256/128K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE ◆ On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port

70V7519

Abstract: IDT70V7519 IDT70V7519S ba6l
Contextual Info: Š HIGH-SPEED 3.3V 256K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ 256K x 36 Synchronous Bank-Switchable Dual-ported SRAM Architecture – 64 independent 4K x 36 banks – 9 megabits of memory on chip

A17R-A0R

Abstract: A17L-A0L 7144
Contextual Info: HIGH-SPEED 1.8V 256/128K x 36 IDT70P3519/99 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V/2.5V/1.8V INTERFACE Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location Low Power High-speed data access

O23R

Abstract: o32l 70V3579 A12L A14L IDT70V3579 IDT70V3579S optl p2 3.5mm
Contextual Info: Š HIGH-SPEED 3.3V 32K x 36 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE IDT70V3579S Features: ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed clock to data access

IDT70T3589

Abstract: IDT70T3599 70T359 70T3589
Contextual Info: HIGH-SPEED 2.5V 256/128/64K x 36 IDT70T3519/99/89S SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed data access

Contextual Info: Š Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ IDT70T651/9S HIGH-SPEED 2.5V 256/128K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE ◆ On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port

B12 IC marking code

Abstract: 70V3599 A12L IDT70V3599 IDT70V3599S
Contextual Info: HIGH-SPEED 3.3V 128K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE PRELIMINARY IDT70V3599S Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed data access

BE5L

Abstract: CYD18S18V18 CYD09S36V18 CYD18S36V18 SKR 175 FullFlex36
Contextual Info: FullFlex FullFlex Synchronous SDR Dual Port SRAM Features Functional Description • True dual port memory enables simultaneous access to the shared array from each port ■ Synchronous pipelined operation with Single Data Rate SDR operation on each port

IDT70T659

Contextual Info: HIGH-SPEED 2.5V 256/128K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed access – Commercial: 10/12/15ns max.

FullFlex36

Contextual Info: FullFlex FullFlex Synchronous DDR Dual-Port SRAM Features • True dual-ported memory allows simultaneous access to the shared array from each port • Synchronous pipelined operation with selectable Double Data Rate DDR or Single Data Rate (SDR) operation on each port

FullFlex36

Contextual Info: PRELIMINARY FullFlex Synchronous DDR Dual-Port SRAM Features • True dual-ported memory allows simultaneous access to the shared array from each port • Synchronous pipelined operation with selectable Double Data Rate DDR or Single Data Rate (SDR) operation on each port

FullFlex36

Contextual Info: FullFlex FullFlex Synchronous DDR Dual-Port SRAM Features • True dual-ported memory allows simultaneous access to the shared array from each port • Synchronous pipelined operation with selectable Double Data Rate DDR or Single Data Rate (SDR) operation on each port

70V659

Abstract: IDT70V657 IDT70V658 70V658 70V657
Contextual Info: HIGH-SPEED 3.3V IDT70V659/58/57S 128/64/32K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM Š Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed access – Commercial: 10/12/15ns max.

IDT70T3589

Abstract: IDT70T3599 70T3589
Contextual Info: HIGH-SPEED 2.5V PRELIMINARY 256/128/64K x 36 IDT70T3519/99/89S SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed data access

FullFlex36

Contextual Info: CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 FullFlex Synchronous SDR Dual Port SRAM FullFlex™ Synchronous SDR Dual Port SRAM Features Functional Description • True dual port memory enables simultaneous access the shared array from each port ■ Synchronous pipelined operation with single data rate SDR