ATM HEADER-ERROR-CHECK MULTIPLE BIT Search Results

IDT77V500

Abstract: IDT79R36100 IDT79RV3041 IDT79RV4640 IOD031 IDT77V400 OP7D 3606
Contextual Info: ATM CELL BASED 8 X 8 NON-BLOCKING SINGLE CHIP SWITCHING MEMORY ADVANCED INFORMATION IDT77V400 Integrated Device Technology, Inc. FEATURES: • Byte Addition or Byte Subtraction for x8 to x16/x32 Utopia conversion capability • Internal header Cyclical Redundancy Check CRC and

MU9C1480A

Abstract: MU9C1480A-90DC Add.dat
Contextual Info: Application Note AN-N9 VPI/VCI Translation and Cell Tagging in ATM With The MU9C1480A LANCAM INTRODUCTION The MUSIC LANCAMs are content-addressable memories CAM originally intended for LAN bridge and router address filtering applications. However, LANCAMs

etm757

Abstract: 5966-1444E ETM759 E4209B E1618A V743 controller area network bus E4219A ETM761 sonet alarms
Contextual Info: 622 Mb/s Optical Line Interface Agilent Technologies Broadband Series Test System E1618A Product Features The Agilent E1618A 622 Mb/s Optical Line Interface LIF is a single slot, single port (1 Tx/ 1 Rx) VXI module for the BSTS that provides access to OC-12c/STM-4c devices.

Contextual Info: Preliminary P/N IBM30CMATPS00PA0AT ATM 2 5 M b p s P CI C on t r ol l e r M o d ul e IBM International Business Machines Corporation, 1997 All Rights Reserved • The ATM 25Mbps PCI Controller is a 32-bit Bus Master, which means REQ64, ACK64, and PAR64 are not implemented, nor are the

OP7D

Abstract: 3606 IDT77155 IDT77V400 IDT77V500 IDT79R36100 IDT79RV3041 IDT79RV4640 IOD031 IOD21
Contextual Info: SWITCHStARTM ATM CELL BASED 8 X 8 NON-BLOCKING SINGLE CHIP SWITCHING MEMORY PRELIMINARY IDT77V400 Integrated Device Technology, Inc. FEATURES • Configurable cell lengths of 52, 53, 54, 55, or 56 bytes can be independently chosen for Input and Output ports

Contextual Info: PHAST-3P Device STM-1/STS-3c SDH/SONET Overhead Terminator with CDB/PPP UTOPIA Interface TXC-06203 FEATURES DESCRIPTION • ATM cells over SDH/SONET - ATM cell delineation - Single-bit error correction and multiple-bit error detection - ATM Scrambler/descrambler option x43 +1

Contextual Info: PHAST-3P Device STM-1/STS-3c SDH/SONET Overhead Terminator with CDB/PPP UTOPIA Interface TXC-06203 TECHNICAL OVERVIEW PRODUCT PREVIEW LINE SIDE Bit-Serial / Byte-Parallel Clock, Data, and Parity Bit-Serial / Byte-Parallel Clock, Data, and Parity Boundary Scan,

100-PIN

Abstract: IDT77V400 IDT77V500 IDT79R36100 IDT79RV3041 IDT79RV4640 PN100-1
Contextual Info: ATM CELL BASED NON-BLOCKING SINGLE CHIP SWITCH CONTROLLER ADVANCED INFORMATION IDT77V500 Integrated Device Technology, Inc. • Available in a 100-pin Thin Plastic Quad Flat Pack TQFP FEATURES: • Single chip controller for IDT77V400 Switching Memory • One IDT77V500 and one IDT77V400 form the core

0x1758

Abstract: dmo 365 r dmo 365 17X17 GR-253 GR-499-CORE XRT79L71 XRT79L71IB CIRCUIT DIAGRAM UPS 775 intel
Contextual Info: XRT79L71 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC JUNE 2007 GENERAL DESCRIPTION The XRT79L71 is a single channel, ATM UNI/PPP Physical Layer Processor with integrated DS3/E3 framing controller and Line Interface Unit with Jitter Attenuator that is designed to support ATM direct

33272P

Abstract: ctet
Contextual Info: xr PRELIMINARY XRT7234 E3 UNI FOR ATM NOVEMBER ‘999 REV. P1.0.0 1.0 SYSTEM DESCRIPTION The XR- T7234 E3 UNI IC for ATM consists of the following functional sections/ blocks. • Transmit Section – Transmit Utopia Interface Block – Transmit Cell Processor Block

0X1F65

Abstract: 0X1121
Contextual Info: xr PRELIMINARY XRT79L71 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION OCTOBER 2005 GENERAL DESCRIPTION The XRT79L71 is a single channel, ATM UNI/PPP Physical Layer Processor with integrated DS3/E3 framing controller and Line Interface Unit with Jitter

Contextual Info: ATM CELL BASED NON-BLOCKING SINGLE CHIP dt) ADVANCED IDT77V500 SWITCH CONTROLLER Integrated De1vice Technology, Inc. • Available in a 100-pin Thin Plastic Quad Flat Pack TQFP) FEATURES: • Single chip controller for IDT77V400 Switching Memory • One IDT77V500 and one IDT77V400 form the core

"error correction algorithm"

Abstract: lasar datasheets 001B GR-253-CORE PM7375 qsaa "network interface cards"
Contextual Info: PMC-Sierra, Inc. APPLICATION NOTE ISSUE 1 PM7375 LASAR-155 LASAR-155 Programmer's Guide PM7375 TM LASAR155 PROGRAMMER'S GUIDE Preliminary Information Issue 1: March, 1996

C3607

Abstract: 100-PIN IDT77155 IDT77V400 IDT77V500 IDT79R36100 IDT79RV3041 IDT79RV4640 PN100-1
Contextual Info: SWITCHStARTM ATM CELL BASED NON-BLOCKING SINGLE CHIP SWITCH CONTROLLER PRELIMINARY IDT77V500 Integrated Device Technology, Inc. without derating for larger switch configurations • Industrial temperature range -40° C to +85° C available • Single +3.3V ± 0.3V power supply

tag 8833

Abstract: Internal diagram of ic 7495 CRC-10 TPAT640
Contextual Info: Product Brief June 2001 TPAT640 High-Speed Switching Protocol Independent ATM Layer Processor PI-ATM Introduction The protocol independent ATM layer processor (PI-ATM) is part of the Agere Systems high-speed switching family of devices. It provides a highly integrated, innovative, and complete VLSI solution for

ternary content addressable memory

Abstract: CY7C0430BV Cypress Ternary Content Addressable
Contextual Info: Designing with Cypress QuadPort CY7C0430BV Backplane Switch Introduction The QuadPort™ is much more than a simple bus matching tool. It is a data transport enabler which gives a designer maximum flexibility in creating a data path architecture which will

POS-PHY ATM format

Contextual Info: Sertopia Device UTOPIA Serializer TXC-05860 DESCRIPTION • In-band UTOPIA and POS-PHY Level 2 operating modes for cell and packet traffic • UTOPIA Level 2, and POS-PHY operating modes for cell and packet traffic • One UTOPIA port up to 800 Mbit/s

Contextual Info: PHY TC-PMD for 25.6 Mbps ATM Networks PRELIMINARY IDT77105 Integrated Device Technology, Inc. FEATURES DESCRIPTION • Performs the PHY-Transmission Convergence (TC) and Physical Media Dependent (PMD) Sublayer functions for 25.6 Mpbs ATM Networks • UTOPIA Level 1 Interface

bit3195

Abstract: dmo 265 8051 interfacing programming examples TTB-11 diode T35 12H XRT7234 XR-T7295E XRT7296 XR-T7296 332102rx
Contextual Info: xr XRT7234 PRELIMINARY E3 UNI FOR ATM NOVEMBER ‘999 1.0 SYSTEM DESCRIPTION The XR-T7234 E3 UNI IC for ATM consists of the following functional sections/blocks. • Transmit Section – Transmit Utopia Interface Block – Transmit Cell Processor Block – Transmit E3 Framer Block

ABP1

Contextual Info: Advance Data Sheet March 1994 , sA TC T Microelectronics T7650 PHOENIX 8-bit Parallel Buffered 2-by-2 Switching Node for Broadband Switching Networks Features • Asynchronous transfer mode ATM cell compati­ ble ■ Crosspoint-buffered, self-routing, 2-by-2 switching

Contextual Info: Sertopia Device UTOPIA Serializer TXC-05860 DATA SHEET PRODUCT PREVIEW The Sertopia™ TXC-05860 UTOPIA serializer is a single-chip solution for broadband communication systems. A pair of Sertopia devices interface two remote UTOPIA ports transparently across a serial link. The Sertopia emulates a

DSLAM configuration AWS

Abstract: rx bc nbk TSC 13003 pcr 465 ATML 18751 circuit BKC International mpc82 bsdl nd1 marking code acm 33221
Contextual Info: MC92520 ATM Cell Processor User’s Manual MC92520UM/D Rev. 0, 12/2000 DigitalDNA and Mfax are trademarks of Motorola, Inc. Information in this document is provided solely to enable system and software implementers to use Motorola microprocessors. There are no express or implied copyright licenses granted hereunder to design or fabricate Motorola integrated circuits or integrated

CHN 803

Abstract: NTK ALARM IC AH52 1F
Contextual Info: PHY TC-PMD USER NETWORK INTERFACE FOR 155 MBPS ATM NETWORK APPLICATIONS ADVANCED INFORMATION IDT77155 In teg rated D evice Technology, Inc. KEY FEATURES • Supports up to 4 PHYs for Multi-PHY connections with 2bit address and 8-bit data using UTOPIA 2 protocol.

Contextual Info: PHY TC-PMD for 25.6 Mbps ATM Networks PRELIMINARY IDT77105 Integrated D evice Technology, Inc. FEATURES DESCRIPTION • Performs the PHY-Transmission Convergence (TC) and Physical Media Dependent (PMD) Sublayer functions for 25.6 Mpbs ATM Networks • UTOPIA Level 1 Interface