OP7D Search Results

4413

Abstract: IDT77155 IDT77V400 IDT77V500 IDT77V550 IDT79R36100 IDT79RV3041 IDT79RV4640 osam marking code
Contextual Info: SECTION 2 IDT77V400 Switching Memory 2.1 IDT77V400 Switching Memory Description The IDT77V400 Switching Memory is designed to provide essential data path functionality for switches, concentrators and expanders in Asynchronous Transfer Mode ATM Networks. The IDT77V400 supports aggregate data throughput at rates up to 1.24 Gbps and has 8192

3606

Contextual Info: PRELIMINARY IDT77V400 SWITCHStAR ATM CELL BASED 8 X 8 NON-BLOCKING SINGLE CHIP SWITCHING MEMORY FEATURES • Configurable cell lengths of 52, 53, 54, 55, or 56 bytes can be independently chosen for Input and Output ports • Byte Addition or Byte Subtraction for x4/x8 to x l 6/x32

IDT77155

Abstract: IDT77V400 IDT77V500 IDT77V550 IDT79R36100 IDT79RV3041 IDT79RV4640 3606
Contextual Info: SWITCHStARTM ATM CELL BASED 8 X 8 PRELIMINARY 1.24Gbps NON-BLOCKING IDT77V400 INTEGRATED SWITCHING MEMORY Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Single chip supports an 8 x 8 port switch at 155Mbps per port Fusion MemoryTM technology utilized to provide the

P07E

Abstract: OP-7E 0P07C op07e OP7D op7c 0P-07C
Contextual Info: OP-07C, OP 0 7D , OP-Û7E U LTR A LO W -O FFSET-VO LTAG E O P ER A TIO N A L A M P LIFIER S D 2 7 5 7 , OCTOBER 1 9 8 3 -R E V IS E D JU NE 1 9 8 8 • Ultra-Low Offset Voltage . . .30 ¿tV Typ OP-07E • Ultra-Low Offset Voltage Temperature Coefficient . . . 0 .3 ^V/°C Typ (OP-07E)

Contextual Info: ATM CELL BASED 8 X 8 NON-BLOCKING SINGLE CHIP ADVANCED INFORMATION IDT77V400 SWITCHING MEMORY Integrated D e v ie TechnoJogy, lie . FEATURES: • Byte Addition or Byte Subtraction fo r x8 to x16/x32 U topia conversion capability • Internal header C yclical R edundancy C he ck CRC and

B1416

Abstract: E1113 1CS MARKING IDT77V400 IDT77V500 IDT77V550 13-bitcell m1416 s156 A1516
Contextual Info: IDT77V400 SwitchStarTM ATM Cell Based 8 x 8 1.2Gbps non-blocking Integrated Switching Memory Features List ! Single chip supports an 8 x 8 port switch at 155Mbps per port ! Central Memory Architecture eliminates Head-of-Line Blocking by sharing the memory array with all ports

Contextual Info: PRELIMINARY IDT77V400 SWITCHStAR ATM CELL BASED 8 X 8 NON-BLOCKING SINGLE CHIP SWITCHING MEMORY In teg ra ted D e v i l e T e c h n o lo g y , l i e . FEATURES • Configurable cell lengths of 52, 53, 54, 55, or 56 bytes can be independently chosen for Input and Output ports

b1416

Abstract: D1416 b14-16 IDT77155 IDT77V400 IDT77V500 IDT77V550 IDT79R36100 IDT79RV3041 IDT79RV4640
Contextual Info: IDT77V400 SwitchStarTM ATM Cell Based 8 x 8 1.2Gbps non-blocking Integrated Switching Memory
Configurable cell lengths of 52, 53, 54, 55, or 56 bytes can
  
Single chip supports an 8 x 8 port switch at 155Mbps per be independently chosen for Input and Output ports

OP7D

Abstract: 3606 IDT77155 IDT77V400 IDT77V500 IDT79R36100 IDT79RV3041 IDT79RV4640 IOD031 IOD21
Contextual Info: SWITCHStARTM ATM CELL BASED 8 X 8 NON-BLOCKING SINGLE CHIP SWITCHING MEMORY PRELIMINARY IDT77V400 Integrated Device Technology, Inc. FEATURES • Configurable cell lengths of 52, 53, 54, 55, or 56 bytes can be independently chosen for Input and Output ports

IDT77V500

Abstract: IDT79R36100 IDT79RV3041 IDT79RV4640 IOD031 IDT77V400 OP7D 3606
Contextual Info: ATM CELL BASED 8 X 8 NON-BLOCKING SINGLE CHIP SWITCHING MEMORY ADVANCED INFORMATION IDT77V400 Integrated Device Technology, Inc. FEATURES: • Byte Addition or Byte Subtraction for x8 to x16/x32 Utopia conversion capability • Internal header Cyclical Redundancy Check CRC and

tle 6366

Contextual Info: SWITCHStAR ATM CELL BASED 8 X 8 PRELIMINARY 1.24Gbps NON-BLOCKING IDT77V400 INTEGRATED SWITCHING MEMORY Features Single chip supports an 8 x 8 port switch at 155Mbps per port Fusion Memory™ technology utilized to provide the performance of SRAM with the economy of DRAM

IDT77V400

Abstract: IDT77V500 IDT77V550 IOD-11 D14-16 3606
Contextual Info: IDT77V400 SwitchStarTM ATM Cell Based 8 x 8 1.2Gbps non-blocking Integrated Switching Memory Features List ! Single chip supports an 8 x 8 port switch at 155Mbps per port ! Central Memory Architecture eliminates Head-of-Line Blocking by sharing the memory array with all ports

IOD17

Abstract: IOD16 IOD22 3606
Contextual Info: IDT77V400 SwitchStarTM ATM Cell Based 8 x 8 1.2Gbps non-blocking Integrated Switching Memory
Configurable cell lengths of 52, 53, 54, 55, or 56 bytes can
  
Single chip supports an 8 x 8 port switch at 155Mbps per be independently chosen for Input and Output ports