APEX20K Search Results

CY7C1302V25

Abstract: CY7C1304V25 APEX20KE QDR cypress burst of two
Contextual Info: Interfacing the QDR with Altera APEX20KE QDR™: An Introduction The evolution of newer systems has increased demands on speed and performance. As a result of this, faster processors have emerged that have increased the demands on memory performance. Newer memory architectures with higher

EP20K1000C

Abstract: EP20K100E EP20K200C EP20K30E EP20K400C EP20K600C EP20K60E apex20k
Contextual Info: APEX20K_04_J.qxd 3.3 02.9.9 3:51 PM ページ 8 APEX Devices システム・レベル・インテグレーションのための 高集積エンベデッド・プログラマブル・ロジック・デバイス KC 2 X APE ring Featu pper yer Co All-La nnect

APEX20KE

Abstract: CY7C1302V25 CY7C1304V25 RPS for atm
Contextual Info: Interfacing the QDR with Altera APEX20KE QDR™: An Introduction The evolution of newer systems has increased demands on speed and performance. As a result of this, faster processors have emerged that have increased the demands on memory performance. Newer memory architectures with higher

HSTL standards

Abstract: SSTL-18 class sstl 15-V AGX52008-1 APEX20KC
Contextual Info: 8. Selectable I/O Standards in Arria GX Devices AGX52008-1.2 Introduction This chapter provides guidelines for using industry I/O standards in Arria GX devices, including: • ■ ■ ■ ■ I/O features I/O standards External memory interfaces I/O banks

TC3024

Abstract: vhdl code hamming vhdl coding for hamming code hamming decoder vhdl code hamming vhdl block diagram code hamming qpsk modulation VHDL CODE vhdl code for block turbo codes TC3014 TC3000
Contextual Info: TurboConcept 1, av. du Technopôle 29280 PLOUZANE FRANCE phone : +33 2 29 00 19 88 fax : +33 2 29 00 18 03 www.turboconcept.com TC3000 Turbo Product Code decoders Introducing turbo product codes with BCH “t=2” codes Customisable bitrate : 7 to 25 Mbits/s

40MHZ

Abstract: APEX20K APEX20KE tcl script ModelSim
Contextual Info: Scripting with Tcl November 1999, ver. 2.0 Introduction Application Note 118 Developing and running tool command language Tcl scripts in the QuartusTM software allows designers to perform a wide range of simple or complex functions, such as compiling a design or writing procedures to

c33 compiler

Abstract: 1Mb x 4 RAM
Contextual Info: PF1130-04 S1C33 Family 32-bit Single Chip Microcomputer • DESCRIPTION The S1C33 Family microcomputer consists of a Seiko Epson original CMOS 32-bit RISC core, ROM, RAM, DMA, timers, SIO, PLL, A/D and other circuits. Featuring high-speed operation, low power consumption, reduced code

B17C

Abstract: teradyne flex tester AGX52001-1 AGX52002-1 AGX52003-1 AGX52004-1 AGX52005-1 AGX52006-1 AGX52007-1 AGX52008-1
Contextual Info: Arria GX Device Handbook, Volume 2 101 Innovation Drive San Jose, CA 95134 www.altera.com AGX5V2-1.2 Copyright 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and

verilog code for amba ahb bus

Abstract: verilog code for amba ahb master excalibur Board
Contextual Info: Excalibur Bus Functional Model User Guide July 2002 Version 1.2 101 Innovation Drive San Jose, CA 95134 408 544-7000 http://www.altera.com A-UG-XBUS-1.2 Excalibur Bus Functional Model User Guide Copyright  2002 Altera Corporation. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all

excalibur APEX development board nios

Abstract: "dual 7 Segment" APEX nios development board dual 7-segment led JP13 altera board
Contextual Info: Nios Embedded Processor Development Board April 2002, ver. 2.1 Data Sheet Introduction This data sheet describes the features and functionality of the Nios CPU development board included in the ExcaliburTM Development Kit, featuring the Nios embedded processor.

APEX20KE

Abstract: ModelSim 5.4e
Contextual Info: Using ModelSim-Altera in a Quartus II Design Flow December 2002, ver. 1.2 Introduction Application Note 204 This application note is a getting-started guide to using ModelSimR-Altera software in AlteraR programmable logic device PLD design flows. Proper functional and timing simulation is important to ensure design

AMBA ahb bus protocol

Abstract: verilog code for ahb bus slave ahb wrapper verilog code excalibur Board
Contextual Info: Excalibur Bus Functional Model User Guide July 2002 Version 1.2 101 Innovation Drive San Jose, CA 95134 408 544-7000 http://www.altera.com UG-XBUS-1.2 Excalibur Bus Functional Model User Guide Copyright  2002 Altera Corporation. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all

A-DS-APEX20K-03

Contextual Info: APEX 20K Programmable Logic Device Family January 2001, ver. 3.3 Features. Data Sheet • Preliminary Information ■ Industry’s first programmable logic device PLD incorporating system-on-a-programmable-chip integration – MultiCoreTM architecture integrating look-up table (LUT) logic,

Contextual Info: Q u a r t u s Programm able Logic Development System Tutorial Altera Corporation 101 Innovation Drive San Jose, CA 95134 408 544-7000 http://www.altera.com Quartus Tutorial Version 1999.10 October 1999 P25-04732-01 Altera, the Altera logo, and MAX+PLUSII are registered trademarks of Altera Corporation in the United States and other

vhdl code for Clock divider for FPGA

Abstract: verilog code divide floating point verilog verilog code for floating point unit IEEE-754 vhdl code of floating point unit APEX20K APEX20KC APEX20KE FLEX10KE
Contextual Info: DFPDIV Floating Point Pipelined Divider Unit ver 2.15 OVERVIEW The DFPDIV uses the pipelined mathematics algorithm to divide two arguments. The input numbers format is according to IEEE754 standard. DFPDIV supports single precision real number. Divide operation was pipelined up to 15 levels. Input data are fed every

verilog code for floating point multiplication

Abstract: verilog code for 32-bit alu with test bench ieee single precision floating point alu in vhdl ieee floating point alu in vhdl CORDIC altera APEX20K APEX20KC APEX20KE DP8051XP FLEX10KE
Contextual Info: DP8051XP Pipelined High Performance 8-bit Microcontroller ver 4.05 OVERVIEW DP8051XP is a ultra high performance, speed optimized soft core of a single-chip 8bit embedded controller dedicated for operation with fast typically on-chip and slow (offchip) memories. The core has been designed

bosch can 2.0B

Abstract: DPRAM FLEX10KE BOSCH CAN vhdl Bosch can Bosch d_can Bosch APEX20K APEX20KC APEX20KE
Contextual Info: DCAN Configurable CAN Bus Controller ver 1.01 ● Last Error Code The DCAN is a stand-alone controller for the Controller Area Network CAN widely used in automotive and industrial applications. DCAN conforms to Bosch CAN 2.0B specification (2.0B Active). Core has simple CPU interface

8051 16bit addition, subtraction

Abstract: verilog code for alu and register and ram and int 80C51 APEX20K APEX20KC APEX20KE DP8051 DP8051CPU DP8051XP FLEX10KE
Contextual Info: DP8051 Pipelined High Performance 8-bit Microcontroller ver 4.03 OVERVIEW DP8051 is an ultra high performance, speed optimized soft core of a single-chip 8bit embedded controller dedicated for operation with fast typically on-chip and slow (offchip) memories. The core has been designed

ALU vhdl code

Abstract: verilog code for serial multiplier 80C51 APEX20K APEX20KC APEX20KE DP80390 DP80390CPU DP8051 FLEX10KE
Contextual Info: DP80390 Pipelined High Performance 8-bit Microcontroller ver 4.02 OVERVIEW DP80390 is an ultra high performance, speed optimized soft core of a single-chip 8bit embedded controller dedicated for operation with fast typically on-chip and slow (offchip) memories. It supports up to 8 MB of linear code and 16 MB of linear data spaces. The

vhdl code for phase shift

Abstract: verilog code for 8 bit shift register vhdl code for spi vhdl code for 8 bit shift register vhdl spi interface DSPIS vhdl code for spi controller implementation on vhdl code for clock phase shift APEX20K APEX20KC
Contextual Info: DSPIS Serial Peripheral Interface –Slave ver 1.01 OVERVIEW The DSPIS is a fully configurable SPI ma slave device, designated to operate with passive devices like memories, LCD drivers etc. The DSPIS allows user to configure polarity and phase of serial clock signal SCK.

verilog code for floating point multiplication

Abstract: vhdl code for cordic cosine and sine vhdl code for cordic VHDL code for floating point addition verilog code for floating point division vhdl code for cordic multiplication program for 8051 16bit square root verilog code for single precision floating point multiplication 8051 16bit addition, subtraction CORDIC sine cosine float altera
Contextual Info: DFPMU Floating Point Coprocessor ver 2.05 OVERVIEW DFPMU is a Floating Point Coprocessor, designed to assist CPU in performing the floating point mathematic computations. DFPMU directly replaces C software functions, by equivalent, very fast hardware operations,

LATTICE 3000 SERIES cpld

Abstract: ATMEL 350 altera 10 k series cpld DPRAM FLASH370 LATTICE 3000 SERIES APEX20K APEX20KC FLEX6000 FLEX8000
Contextual Info: FPGA/CPLD CONVERSION SERVICE ULC C O S T S AV I N G S WITH NO RISK P L U G A N D S AV E COST REDUCTION In today's market, cost reduction is a must to MADE EASY maintain competitiveness. New products Equivalent complexity, much smaller FPGA, 252 mm² need to be designed fast, before the competition catches up. FPGA/CPLD usage provides early feedback to designers. This

SHA-256 Cryptographic Accelerator

Abstract: verilog code for 128 bit AES encryption CS5311 SHA-1 using vhdl SHA-256 verilog code for 8 bit AES encryption verilog code for aes encryption SHA-512 SHA256 verilog code for 32 bit AES encryption
Contextual Info: CS5310/11/12 Standard Hash Algorithm SHA-1 & SHA-2 Cores TM Virtual Components for the Converging World The CS5310/11/12 Hashing Cores are designed to achieve data authentication in digital broadband, wireless, and multimedia systems. These high performance application specific silicon cores support the Secure Hash

verilog code for 32 bit AES encryption

Abstract: vhdl code for aes decryption vhdl code for AES algorithm verilog code for image encryption and decryption verilog code for 128 bit AES encryption vhdl code for aes vhdl code for aes image encryption and decryption vhdl code for aes 192 encryption block diagram simplex Voice encryption
Contextual Info: CS5265/75 TM AES Simplex Encryption/Decryption Cores Virtual Components for the Converging World The CS5265 and CS5275 Simplex AES encryption/decryption1 cores are designed to achieve data privacy in digital broadband, wireless, and multimedia systems. These high performance application specific cores support