AM2964 Search Results

ef3r

Abstract: bf5r 12MC
Contextual Info: Am2964B/Am2964C Am2964B/Am2964C* Dynamic Memory Controller ADVANCED INFORMATION DISTINCTIVE CHARACTERISTICS Dynamic Memory Controller for 16K and 64K MOS dynamic RAMs 8-Bit Refresh Counter for refresh address generation, has clear input and terminal count output

64K RAM

Contextual Info: CFA0640A CFA0640A 2964 GENERAL DESCRIPTION: AM2964-DYNAMIC MEMORY CONTROLLER CFA0640A is designed to be fully compatible with AM2964 bit-slice Dynamic RAM Controller. In CFA0640A, one extra input, 64KRAM, is tied to LOW; in AM2964, A15 is pulled up to +12V through a

Contextual Info: a F in a l Am2964B Advanced Micro Devices Dynamic Memory Controller DISTINCTIVE CHARACTERISTICS • • • Dynamic Memory Controller for 16K and 64K MOS dynamic RAMs 8 -Bit Refresh Counter for refresh address generation, has clear input and terminal count output

AM2964B

Abstract: 16-32K
Contextual Info: Am2964B Advanced Micro Devices Dynamic Memory Controller DISTINCTIVE CHARACTERISTICS Dynamic Memory Controller for 16K and 64K MOS dynamic RAMs 8 -Bit Refresh Counter for refresh address generation, has clear input and terminal count output Refresh Counter terminal count selectable at 256 or 128

Am2964

Abstract: Dynamic Memory Refresh Controller
Contextual Info: Am2964 Dynam ic Memory Controller IN DEVELOPMENT DISTIN CTIVE C H A R A C T E R IST IC S FU NCTIONAL D ESC RIPT IO N • Dynamic Memory Controller for 16K and 34K M O S dynamic RAMs • 8-Bit Refresh Counter for refresh address generation, has clear input and terminal count output

bit-slice

Contextual Info: CFA0640A CFA0640A CFS0640A DRAM Controller DESCRIPTION: CFA0640A is fully compatible with the AM2964 bit-slice dynamic RAM controller. One extra input, 64KRAM, is added to select the 64K or 16K dynamic memory. To use 16K RAMs, CFA0640A requires that 64KRAM be tied to low, while AM2964 requires that

cason

Abstract: amd 2900 64KRAM
Contextual Info: GFA0640A GFA0640A GFA0640A D RAM CONTROLLER GENERAL DESCRIPTION: THE GFA0640A IS DESIGNED TO BE FULLY COMPATIBLE WITH THE AM2964 BIT SLICE DYNAMIC RAM CONTROLLER. FOR THE GFA0640A, ONE EXTRA INPUT, 64KRAM, IS ADDED TO SELECT EITHER THE 64K OR 16K DYNAMIC MEMORY. FOR A DETAILED FUNCTIONAL DESCRIPTION,

AmZ8000

Abstract: CD0018
Contextual Info: Am8127 AmZ8000 Clock Generator DISTINCTIVE CHARACTERISTICS High-drlve high-level clock output Special output provides clock signal matched to re­ quirements of AmZBOOO* CPU 4MHz and some 6 MHz applications , MMU and DMA devices. Synchronized WAIT state and time-out controls

AMD 20 PIN CERDIP

Abstract: AM2965/B2A
Contextual Info: Am2965/Am2966 Advanced Micro Devices Octal Dynamic Memory Drivers with Three-State Outputs DISTINCTIVE CHARACTERISTICS Controlled rise and fall characteristics Internal resistors provide symmetrical drive to HIGH and LOW states, eliminating need for external series

amd 14 pin cerdip driver

Contextual Info: a Am2965/Am2966 Octal Dynamic Memory Drivers with Three-State Outputs Advanced Micro Devices DISTINCTIVE CHARACTERISTICS Controlled rise and fall characteristics Internal resistors provide symmetrical drive to HIGH and LOW states, eliminating need for external series

2B0365

Abstract: 74ls244 latch ic Z8127 z80 multibus Am286
Contextual Info: Am8163/Am8167 A m 816 3 /A m 816 7 Dynamic Memory Timing, Refresh and EDC Controllers DISTINCTIVE CHARACTERISTICS • Complete CPU to dynamic RAM control interface • R A S /M S E L/C A S Sequencer to eliminate delay lines • Complete EDC/data path controls for W ord/Byte read

Contextual Info: Am8163/Am8167 Am8163/Am8167 Dynamic Memory Timing, Refresh and EDC Controllers DISTINCTIVE CHARACTERISTICS • • • • Complete CPU to dynamic RAM control Interface RAS/MSEL/óÀS Sequencer to eliminate delay lines Complete EDC/data path controls for Word/Byte read

cq 721

Abstract: am26ls31 27LS00 TRANSISTOR SUBSTITUTION Amdasm am2911pc 25S558 STK 025 power amplifier GE semiconductor data handbook am29811adc-b
Contextual Info: í i í i í i n z ta a a a a a a a a a a a r n a a a a a a a a a a a a a i: 33a a a a a a n a a a a a ; a a a a a a a a n a a iia a r r ia a a a a a n a a iia a a r l a n g a s í i í i í i * i¿ w n r w a s a jn sü n n a n a n n n n íiíi íiíiíi n n s n n n

am29203 "evaluation board"

Abstract: L0512 MV8000 TTL catalog CL1101 8038 ic tester circuit diagram tl 2345 ml gcr encoder parallel bus arbitration 30GRAMMABLE
Contextual Info: PROGRAMMABLE ’ROGRAMMABLE 30GRAMMABLE L DGRAMMABLE LG 3RAMMABLE LOG ÏRAMMABLE LOGI ÌAMMABLE LÄGIC a Advanced Micro Devices Programmable Array Logic Handbook Prepared by the Product Planning and Applications Staff at Advanced M icro Devices, Inc. Brad Kitson, Editor

Contextual Info: Am8127 AmZ8000 Clock Generator DISTINCTIVE CHARACTERISTICS Hlgh-drive high-level clock output Four TTL-level clocks Special output provides clock signal matched to re­ quirements of AmZSOOO* CPU 4MHz and some 6 MHz applications , MMU and DMA devices. Generates synchronized TTL compatible clocks at

LM 8002

Abstract: z8000 AMZ8000
Contextual Info: Am8127 Am 8127 AmZ8000 D ock Generator DISTINCTIVE CHARACTERISTICS • Four TTL-tevel clocks Hlgh-drive high-level clock output Special output provides clock signal matched to re­ quirements of AmZ8000* CPU 4MHz and some 6MHz applcations . MMU and DMA devices.

mip 291

Abstract: DIAGRAM pal 005a ic MIP 291 AM29116 X0953 29LS18 PAL16L8 LDPC encoder AM29xx PAL16R8 algorithm amd
Contextual Info: a Am29116 A Microcoded Instruction Processor Based On The Am29116 Application Note Bv Robert e . Anderson ADVANCED MICRO DEVICES The MIP Board: A Microcoded 1-Code Processor Based on the Am29116 A. David Milton, Mitel Robert E. Anderson, AMD March, 1985. Table Of Contents

10BT

Abstract: 2964B
Contextual Info: MAY 86 This Material C o p y r i g h t e d B y Its R e s p e c t i v e M a n u f a c t u r e r 1. SCOPE 1.1 Scope. This drawing describes device requirements for class B microcircuits in accordance with 1.2.1 of MIL-STD-883, "Provisions for the use of MIL-STD-883 In

amd am2 pinout

Abstract: AL S244 pinout AM2 AMD 74S240 74S244 S240 amd 14 pin cerdip driver
Contextual Info: il Am2965/Am2966 Octal Dynamic Memory Drivers with Three-State Outputs Advanced Micro Devices DISTINCTIVE CHARACTERISTICS Controlled rise and fall characteristics Internal resistors provide symmetrical drive to HIGH and LOW states, eliminating need for external series

MPR-502

Abstract: 9016dpc AM2960DC
Contextual Info: a ? P # >* V>?V Ä ^ -0 ° ' \G ° h P r# O <g> -s O r ,o O A <$• K 0< ^ P - rO N * J§ > . <<& '" * ^ & ^ *ä *w nnnnnnnnnnnnnnnnnnnnnnnn nnnnnnnnnnnnnnnnnnnnnnnn nnnnnnnnnnnnnnnnnnnnnnnn nnnnnnnnnnnnnnnnnnnnnnnn CIil nn nei nn nn nn nn nn nn nn nn nn

amd AM2 pinout

Abstract: 2j2a AL S244 pinout AM2 AMD 74S240 74S244 S240 CD001440 AMD 20 PIN CERDIP
Contextual Info: il Am2965/Am2966 Octal Dynamic Memory Drivers with Three-State Outputs Advanced Micro Devices DISTINCTIVE CHARACTERISTICS Controlled rise and fall characteristics Internal resistors provide symmetrical drive to HIGH and LOW states, eliminating need for external series

AM9064-15

Abstract: AM9064-15PC am9064 AM9064-10 R/Detector/"Detector IC"/"CD"/Am2964B/Am9064-15
Contextual Info: Am9064 65,536 x 1 Dynamic RAM DISTINCTIVE CHARACTERISTICS High speed RAS access of 100 and 120ns Single +5V ±10% power supply Low power 22mW standby - 330mW active — 220ns cycle time - 385mW active — 190ns cycle time Read, Write, Read-Modify-Write, Page-Mode and RASOnly refresh capability

str f 6167

Abstract: amz8127 str 6167 supi 3 ls z80b Am8001 AM8163 IC HS 8167 z80 multibus 74LS240
Contextual Info: Am8163/Am8167 A m 8 1 6 3 /A m 8 1 6 7 Dynamic Memory Timing, Refresh and EDC Controllers DISTINCTIVE CHARACTERISTICS EDC error flag latches for error logging under software control Two timing configurations support a broad range of processors Z80, Z8000, 8086, 8088, MC68000

AMZ8000

Abstract: DF000380 AmZ8001/AmZ8002
Contextual Info: Am8127 Am8127 Am Z8000 C lo c k G e n e ra to r DISTINCTIVE CHARACTERISTICS High-drlve high-level clock output Special output provides clock signal matched to re­ quirements of AmZ8000* CPU 4MHz and some 6MHz applications , M MU and DMA devices. Synchronized WAIT state and time-out controls