ADSP Search Results

7273B

Contextual Info: SSRAM AS5SS256K18 256K x 18 SSRAM PIN ASSIGNMENT Top View Synchronous Burst SRAM, Flow-Through 100-pin TQFP SA SA CE\ CE2 NC NC bwB\ BWa\ CE2\ VDD VSS CLK GW\ BWE\ OE\ ADSC\ ADSP\ ADV\ SA SA FEATURES VDD NC VSS DQb DQb VDDQ VSS DQb DQb DQPb NC VSS VDDQ NC

AS5SP512K36DQ

Contextual Info: SSRAM A A CE1\ CE2 BWd\ BWc\ BWb\ BWa\ CE3\ VDD VSS CLK GW\ BWE\ OE\ ADSC\ ADSP\ ADV\ A A AS5SP512K36DQ Plastic Encapsulated Microcircuit Symbol tCYC tCD tOE 200Mhz 5.0 3.0 3.0 166Mhz 6.0 3.5 3.5 133Mhz 7.5 4.0 4.0 Units ns ns ns 81 84 82 83 85 87 86 89 88

ADSP-21489 user manual

Abstract: ADSP-21487 sharc ADSP-214xx FFT Accelerator medialb ADSP-21160 ADSP-21161 ADSP-21489 ADSP21487 sharc iir filter IBIS Model diode
Contextual Info: SHARC Processor SUMMARY The ADSP-2148x processors are available with unique audiocentric peripherals, such as the digital applications interface, serial ports, precision clock generators, S/PDIF transceiver, asynchronous sample rate converters, input

BC136

Abstract: ADSP-21160 ADSP-21161 ADSP-21362 ADSP-21363 ADSP-21364 ADSP-21365 ADSP-21366 key board mtm 8 pins key board mtm
Contextual Info: SHARC Processors SUMMARY DEDICATED AUDIO COMPONENTS High performance 32-bit/40-bit floating point processor optimized for high performance audio processing Single-instruction, multiple-data SIMD computational

TDC1009J

Abstract: TDC1009 TDC-1009J adsp1009td ADSP-1009 adsp-1009kd ADSP-1009JD ADSP-1009JX ADSP-1009KX ADSP-1009SX
Contextual Info: ANALOG DEVICES 12x12-Bit CMOS Multiplier/Accumulator ADSP-1009 FEATURES 12 x 12-Bit Parallel M ultiplication/A ccum ulation 150m W P ow er Dissipation w ith C M O S Technology 130ns M ultiply/A ccum ulate Tim e Im proved TDC1009J Second Source A vailable in 64-Pin Ceram ic DIPs, or 68-Term inal

adsh 13

Abstract: intel 80486 CY7C1031 CY7C1032 VXXXX
Contextual Info: CY7C1031 CY7C1032 PRELIMINARY ?CYPRESS Functional Description continued Single Write Accesses Initiated by ADSP This access is initiated when the following conditions are satisfied at clock rise: (1) is LOW and (2) AD5P is LOW. ADSP-triggered write cycles are completed in two clock periods. The address at Ao

transistor SMD BR21

Abstract: SMD Transistor W08 adsp-21369ksz smd w04 74 smd code t04 smd code W06 transistor SMD W06 sMD .v05 smd transistor w04 SMD Transistors w06 56
Contextual Info: a SHARC Processors ADSP-21367/ADSP-21368/ADSP-21369 SUMMARY Code compatible with all other members of the SHARC family The ADSP-21367/ADSP-21368/ADSP-21369 are available with a 333 MHz core instruction rate with unique audiocentric peripherals such as the digital audio interface, S/PDIF

ADSP-2100

Abstract: PROM BURNER ADDS-2110 dma13 ADSP-2100A ADSP-2100AJG ADSP-2100AKG ADSP-2100JG ADSP-2100JP ADSP-2100KG
Contextual Info: ANALOG DEVICES FEATURES Pin- and Code-Com patible DSP Microprocessors ADSP-2100, 6.144M Hz and 8.192M Hz ADSP-2100A, 10.24M Hz and 12.5MHz Separate Program and Data Buses, Extended Off-Chip Single-Cycle Direct Access to 16K x 16 of Data M em ory Single-Cycle Direct Access to 32K x 24 of Program

ADSP-21000

Abstract: ADSP-21020 ADSP-21060 ADSP-21062 ADSP-21062L tddg
Contextual Info: a ADSP-2106x SHARC DSP Microcomputer Family ADSP-21062/ADSP-21062L SUMMARY High Performance Signal Processor for Communications, Graphics and Imaging Applications Super Harvard Architecture Four Independent Buses for Dual Data Fetch, Instruction Fetch and Nonintrusive I/O

H-a16t

Abstract: ADSP-2191M HA16 Peripheral interface 8255 pinout MO-205-AC adsp-2191-mbst-140
Contextual Info: a DSP Microcomputer ADSP-2191M PERFORMANCE FEATURES 6.25 ns Instruction Cycle Time, for up to 160 MIPS Sustained Performance ADSP-218x Family Code Compatible with the Same Easy to Use Algebraic Syntax Single-Cycle Instruction Execution Single-Cycle Context Switch between Two Sets of Computation and Memory Instructions

ADSP-21062

Abstract: ADSP-21062L ADSP-21065L
Contextual Info: a Computer Products Division ADSP-21062 & ADSP-21062L Anomaly List for Revision 3.0 June 27, 2000 These anomalies represent the currently known differences between the revision 3.0 ADSP21062/ADSP-21062L and the functionality specified in the ADSP-21062 data sheet dated April

GS832018GT-225I

Abstract: GS832036GT-250I 36T2 GS832018 GS832018T-166 GS832018T-200 GS832018T-225 GS832018T-250 GS832032 GS832036
Contextual Info: Preliminary GS832018/32/36T-250/225/200/166/150/133 250 MHz–133 MHz 2.5 V or 3.3 V VDD 2.5 V or 3.3 V I/O 2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs 100-Pin TQFP Commercial Temp Industrial Temp Features cycles can be initiated with either ADSP or ADSC inputs. In

addressing mode in core i7

Abstract: ADSP-21060 ADSP-21060L ADSP-21065L
Contextual Info: a Computer Products Division ADSP-21060 & ADSP-21060L Anomaly List for Revision 2.1 June 27, 2000 These anomalies represent the currently known differences between the revision 2.1 ADSP21060/ADSP-21060L and the functionality specified in the ADSP-21060 data sheet dated

73D13

Abstract: AD73322 ADSP-2100 ADSP-2181 ADSP-2188M ADSP-2189M load program on ADSP-2189M
Contextual Info: a DSP Microcomputer ADSP-2188M System Interface Flexible I/O Structure Allows 2.75 V or 3.3 V Operation; All Inputs Tolerate up to 3.6 V Regardless of Mode 16-Bit Internal DMA Port for High-Speed Access to On-Chip Memory Mode Selectable 4 MByte Memory Interface for Storage of Data Tables

ADSP-21535PKB-300

Abstract: EC38J ADSP-21535 Blackfin dsp 131070
Contextual Info: PRELIMINARY TECHNICAL DATA a ADSP-21535 Preliminary Technical Data SUMMARY 300 MHz High-Performance Blackfin DSP Core Two 16-Bit MACs, Two 40-Bit ALUs, Two 40-Bit Accumulators, Four 8-Bit Video ALUs, and a 40-Bit Shifter RISC-Like Register and Instruction Model for Ease of

79L05

Abstract: AD7840JP 79L05 voltage regulator AD7840 AD7840JN AD7840KN ADSP-2100 TMS32010 TMS32020 ADG201
Contextual Info: a FEATURES Complete 14-Bit Voltage Output DAC Parallel and Serial Interface Capability 80 dB Signal-to-Noise Ratio Interfaces to High Speed DSP Processors e.g., ADSP-2100, TMS32010, TMS32020 45 ns min WR Pulse Width Low Power – 70 mW typ. Operates from ؎5 V Supplies

SPORT

Abstract: ADSP-2106x ADSP-21062 ADSP-21062L ADSP-21065L
Contextual Info: a Computer Products Division ADSP-21062 & ADSP-21062L Anomaly List for Revision 2.0 & 2.1 June 27, 2000 These anomalies represent the currently known differences between the revisions 2.0 & 2.1 ADSP-21062 and the functionality specified in the ADSP-2106x data sheet dated April 1998 and

Contextual Info: JON 4 ANALOG ► DEVICES FEATURES Complete 50 MHz DSP Microcomputer ADSP-2100 Code & Function Compatible 2K Words of Program Memory RAM 1K Word of Data Memory RAM Separate Program and Data Buses On-Chip Dual Purpose Program Memory for Both Instruction and Data Storage

ADSP-2181

Contextual Info: ANALOG DEVICES DSP Microcomputer ADSP-2181 FEATURES PERFORMANCE 25 ns Instruction Cycle Time from 20 MHz Crystal @ 5.0 Volts 40 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in

Contextual Info: ANALOG DEVICES DSP Microcomputer ADSP-21065L SDRAM Controller for Glueless Interface to Low Cost External M em ory @ 66 MHz 64M Words External Address Range 12 Programmable I/O Pins and T w o Timers w ith Event Capture Options Code-Com patible w ith ADSP-2106x Family

Contextual Info: ANALOG DEVICES □ 24 X 24-Bit CMOS Multiplier ADSP-1024A FEATURES 24 x 24-Bit Parallel Multiplication 95ns Multiply Time 450mW Power Dissipation with TTL-Compatible CM OS Technology Twos-Complement Data Format Rounding Options at Three Positions Left-Shifts of 0, 1, or 2 Bits on Output

Contextual Info: ADSP-2106x SHARC DSP Microcomputer Family ADSP-21062/ADSP-21060 ANALOG DEVICES SUMMARY High Performance Signal Processor for Communica­ tions, Graphics, and Imaging Applications Super Harvard ARchitecture Computer SHARC — Four Independent Buses for Dual Data Fetch,

Contextual Info: ANALOG DEVICES □ 32/40-Bit IEEE Floating-Point DSP Microprocessor ADSP-21020 FE A T U R E S Superscalar IEEE Floating-Point Processor Off-Chip Harvard Architecture M axim izes Signal Processing Performance 30 ns, 33.3 M IP S Instruction Rate. Single-Cycle

Contextual Info: ADSP-21060 Industrial SHARC DSP Microcomputer Family ADSP-21060C/ADSP-21060LC ANALOG DEVICES SU M M A R Y High Performance Signal Processor for Com munica­ tions, Graphics, and Im aging Applications Super Harvard Architecture Four Independent Buses for Dual Data Fetch,