ACTEL 1020 DATASHEET Search Results

RTAX2000

Abstract: schematic diagram 2 sc 1020 RTAX1000 RTAX250 Synplify tmr RTAX2000S
Contextual Info: A dv an c ed v0 .5 RTAX-S RadTolerant FPGAs Designed for Space • • • • • • • • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETth > 60 MeV-cm2/mg – SEU Rate < 10-10 Errors/Bit-Day in Worst-Case

APA300-PQ208

Abstract: AC247 macro APA300 APA30
Contextual Info: Application Note AC247 Macro Constraint Usage in ProASICPLUS Design Flow Introduction The use of macro constraints offers designers increased performance of sub-blocks and greater control over the configuration and placement of these individual blocks in their design. A macro constraint

ACTEL 1020B

Abstract: SIGNAL PATH designer actel 1020
Contextual Info: Application Note Global Clock Networks in Actel Antifuse Devices System performance is one of the most important characteristics of a design. As a result, designers put a lot of effort to improve clock speed. Clock skew is often a limiting factor in attaining maximum performance, forcing

Actel a1280

Abstract: VKS FPGA CQFP 172 actel 1020 A1020 smd TRANSISTOR 5962-9215601MXA 5962-9096503MTC equivalent transistor A1020 y 7 b Actel A1020 ACTEL A1010 actel 1020 datasheet
Contextual Info: Military Field Programmable Gate Arrays Features ACT 3 Features • Highly Predictable Performance with 100 Percent Automatic Placement and Routing • Device Sizes from 1200 to 10,000 gates up to 25,000 PLD equivalent gates • Up to 4, Fast, Low-Skew Clock Networks

TRANSISTOR smd A01B

Abstract: A04A SMD 1188AA A1020A-CQ84B SMD PLCC 44PIN MECHANICAL DRAWING 4 bit identity comparator actel a1240 5962-9096501MUX smd transistor s71 44t smd transistor
Contextual Info: actel 53E corp ]> 0 n 2 4 ‘i b Q 0Ü G4 A7 STT M A C T ACT 1 and ACT 2 Military Field Programmable Gate Arrays ACT 1 Features ACT 2 Features • Up to 2000 Gate Array Gates 6000 PLD/LCA™ equivalent gates • Up to 8000 Gate Array Gates (20,000 PLD/LCA™ equivalent gates)

ix741

Abstract: ix2684 AC192 APA1000 n608 SIGNAL PATH designer
Contextual Info: Application Note AC192 Floorplanning ProASIC /ProASICPLUS Devices for Increased Performance Introduction to Floorplanning This application note provides tips and techniques for floorplanning ProASIC and ProASICPLUS devices using Designer. Through floorplanning, you can constrain the placement of important modules in your

Contextual Info: Advanced v1.0.1 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 SEU Hardened Flip-Flops Eliminate Software TMR Necessity LETth > 40, GEO SEU Rate < 10–10

TM101

Contextual Info: Advanced v1.2.3 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 SEU Hardened Flip-Flops Eliminate Software TMR Necessity LETth > 40, GEO SEU Rate < 10–10

A1020 Y

Abstract: smd transistor E5 GHL 88
Contextual Info: Military Field Programmable Gate Arrays Features A C T 3 Features • Highly Predictable Performance with 100 Percent Automatic Placement and Routing • Highest-Performance, Highest-Capacity FPGA Family • System Performance to i( MHz over Military Temperature

ACTEL CCGA 624 mechanical

Abstract: 208-Pin CQFP Actel a54sx72a tid CCGA -CG 472
Contextual Info: v2 . 2 RTSX-S RadTolerant FPGAs Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case

Contextual Info: v2 . 1 RTSX-S RadTolerant FPGAs Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case

A54SX72* radiation

Abstract: cg624 A54SX72A actel 1020 datasheet RT54SX72S RT54SX-S TM1019 HiRel a54sx72a unused
Contextual Info: Advanced v1.4 RT54SX-S RadTolerant FPGAs for Space Applications S p ec i a l F e a tu r es fo r S p ac e • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 SEU Hardened Flip-Flops Eliminate Software TMR Necessity LET th > 40, GEO SEU Rate < 10–10

rt54sx32su

Abstract: RTSX72 RTSX32SU RTSX72-S
Contextual Info: Advanced v0.1 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case

RTSX32su

Abstract: RTSX32SU CQ84 RTSX72SU
Contextual Info: v2.0 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case

RTSX32SU CQ84

Abstract: Silicon Sculptor II RTSX32SU actel 1020
Contextual Info: v2.1 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case

RTSX32SU

Abstract: RTSX32SU CQ84 Actel a54sx72a tid RTSX72SU RTSX-SU actel 1020 Silicon Sculptor II actel 1020 datasheet RT54SX E11213
Contextual Info: v2.2 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case

HiRel a54sx72a unused

Contextual Info: Advanced v1.6 RTSX-S RadTolerant FPGAs for Space Application S p ec i a l F e a tu r es fo r S p ac e • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 SEU Hardened Flip-Flops Eliminate Software TMR Necessity LET th > 40, GEO SEU Rate < 10–10

RTSX32su

Abstract: Actel a54sx72a tid Silicon Sculptor II
Contextual Info: v2.2 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case

HiRel a54sx72a unused

Contextual Info: Advanced v1.3 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 SEU Hardened Flip-Flops Eliminate Software TMR Necessity LET th > 40, GEO SEU Rate < 10–10

Contextual Info: ACT 1 and A C T 2 Military Field P rogram m able G ate Arrays ACT 1 Features ACT 2 Features • Up to 2000 Gate Array Gates 6000 PLD/LCA™ equivalent gates • Replaces up to 53 TTL Packages • Replaces up to 17 20-Pin PAL Packages • Design Library with over 250 Macros

RTAX2000

Abstract: footprint cqfp 280 RTAX1000S actel cqfp 84
Contextual Info: A dv an c ed v0 .5 RTAX-S RadTolerant FPGAs Designed for Space • • • • • • • • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETth > 60 MeV-cm2/mg – SEU Rate < 10-10 Errors/Bit-Day in Worst-Case

A1020A-CQ84B

Abstract: actel package mechanical drawing 5962-9096501MXX TA273 actel a1240 A1020APG84B smd transistor l7 A1020A-JQ84B DEC4X16A "alu 4 bit"
Contextual Info: ACT 1 and ACT 2 Military Field Programmable Gate Arrays ACT 1 Features ACT 2 Features • Up to 2000 Gate Array Gates 6000 P L D / L C A ™ equivalent gates • Up to 8000 Gate A rray Gates (20,000 P L D /L C A ™ equivalent gates) • Replaces up to 53 T T L Packages

EM-553 motor

Abstract: UT16AD40P BUS-8553 CD4583 spw 068 power supply spw 068 UT8QNF8M UT63M143 rtax2000 UT0.6uCRH
Contextual Info: A passion for performance. Aeroflex Microelectronic Solutions Digital, Analog, Power, RFMW, Motion…Solutions for HiRel Applications Product Short Form January 2012 Aeroflex Microelectronic Solutions Product Short Form Aeroflex Microelectronic Solutions is comprised of ten divisions – Colorado Springs, Gaisler, Motion

RTSX32SU CQ84 PROTO

Abstract: RTSX32SU CQ84 RTSX72SU1 SOC 8A fuse smd RTSX32su CG624 thermal expansion
Contextual Info: Revision 9 RTSX-SU Radiation-Tolerant FPGAs UMC Designed for Space • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single Event Upsets (SEU) to LETth > 40 MeVcm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case