ATBL723 Search Results

Contextual Info: t TEXAS INSTR LOGIC ESE D • aTbl723 ODflti44fc, 7 ■ S N 54H C 75, S N 74H C 7S 4 -B IT B IS TA B LE LA TC HES " P & '0 7 - & \ U20B4, DECEMBER 1982 - REVISED SEPTEMBER 1987 S N S 4 H C 7 S . . . J PACKAGE SN 74H C 75 . . . D OR N P A C K A G E (TOP VIEW)

SN74HC237

Contextual Info: TEXAS INSTR LOGIC - 2SE D • aTbl723 Q0abb2fl 2 ■ SN54HC237, SN74HC237 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES _02 8 0 4 , MARCH 19S4-REVIS6D JUNE 1989 SN54HC237 . , . J PACKAGE SN74HC237 . . . D< OR N PACKAGE

D3S59

Abstract: 75365 74ACT16864 54ACT16864 RTOB 1b8c
Contextual Info: TEXAS INSTR LOGIC B'IE D aTbl723 Düti04M2 ô • T I I 3 54AC16864, 54ACT16864 74AC16864, 74ACT16864 18-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS TK>237— 03559, JUNE 1990 Members of Texas Instruments Wldebus 54AC16864, 54AÇT16864 . W D P A C K AG E

Contextual Info: TEXAS INSTR 0=^1723 oaaBü? 1 5SE D LOGIC SN54ALS131, SNB4AS131A, SN74ALS131, SN74AS131A 3-LINE TO 8-LINE DECODERSIDEMULTIPLEXERS WITH ADDRESS REGISTERS r-<U.-2('55 D 2 6 6 1 , A PRIL 1 9 8 2 - R E V IS E D M AY 1986 SN54ALS131, SN54AS131A . . . J PACKAGE

HAI 7203

Abstract: ACT8847 74ACT8847 SN74 multiplier
Contextual Info: TEXAS INSTR LOGIC SSE D 0^1723 GQÖS7G3 7 SN74ACT8847 64-Bit Floating Point Unit • Meets IEEE Standard for Single- and DoublePrecision Formats • Performs Floating Point and Integer Add, Subtract, Multiply, Divide, Square Root, and Compare • 64-Bit IEEE Divide in 11 Cycles, 64-Bit Square

74AC11000

Abstract: D2957 1B-116
Contextual Info: 54AC11000, 74AC11000 QUADRUPLE 2-INPUT POSITIVE-NAND GATES D2957. APRIL 1987 - REVISED APRIL 1993 F low -Through A rch itecture O ptim izes PCB Layout S4AC11000 . . . J PACKAGE 74AC11000 . . . D OR N PACKAGE TOP VIEW Center-Pin V ^ c and GND Configurations

SN54ABT16601

Abstract: SN74ABT16601
Contextual Info: SN54ABT16601, SN74ABT16601 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS _ Members of the Texas Instruments Widebus Family State-of-the-Art EPIC-UB™ BiCMOS Design Significantly Reduces Power Dissipation UBT™ Universal Bus Transceiver

SN54ABT16823

Abstract: SN74ABT16823
Contextual Info: SN54ABT16823, SN74ABT16823 18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SCBS217A- JUNE 1 9 9 2 - REVISED JULY 1994 Members of the Texas Instruments Wldebus Family State-of-the-Art EPIC-llB™ BiCMOS Design Significantly Reduces Power Dissipation

DOT3111

Abstract: SN54ABT5402 SN74ABT5402 0CH311Q
Contextual Info: fn b l? 2 3 0CH311Q 5 7 4 • T I I 3 SN54ABT5402, SN74ABT5402 12-BIT LINE/MEMORY DRIVERS WITH 3-STATE OUTPUTS SCBS100A- D3978, JANUARY 1992 - REVISED OCTOBER 1992 Output Ports Have 25-ii Series Resistors, So No External Resistors Are Required State-of-the-Art EP/C-Hfl BiCMOS Design

Contextual Info: 74AC11652 OCTAL BUS TRANSCEIVER AND REGISTERS WITH 3-STATE OUTPUTS SCAS088A - DECEMBER 1989 - REVISED APRIL 1996 • Independent Registers and Enables for A and B Buses DW PACKAGE TOP VIEW • Multiplexed Real-Time and Stored Data • Inverting Data Paths

Contextual Info: 54ACT11162,74ACT11162 SYNCHRONOUS 4-BIT DECADE COUNTERS SCAS169-D3456, MARCH 1990-REVISED DECEMBER 1991 I • Inputs Are TTL-Voltage Compatible • • Internal Look-Ahead for Fast Counting V • Carry Output for N-Bit Cascading ' • Fully Synchronous Operation for Counting

16-Bit Microprocessors

Abstract: 16-1 multiplexer explain d54j YJ 1100 6
Contextual Info: TEXAS INSTR LOGIC 1ÔE D • 0^1723 GGa023b T B SN74ACT29C116A, SN74ACT29C116-1 16-BIT MICROPROCESSORS D3219, FEBRUARY 1989 • 1 /tm EPIC (Enhanced Performance Implanted CMOS) CMOS Technology • 3 2 x 1 6-Bit Register File Can Be W ritten and Read During a Single Cycle

74AS885

Contextual Info: TEXAS INSTR LOGIC 2SE D • 6*^1723 (3063533 1 ■ SN54AS885, SN74AS88S 8-BIT MAGNITUDE COMPARATORS T -4 5 -A D2661. DECEMBER 1982-REVISED MARCH 1985 S N 5 4 A S 8 S 6 _ J T PACKAGE S N 7 4 A S 8 8 S _ DW OR NT PACKAGE Package Options Include Plastic "Sm all

Contextual Info: SN54ALS374A, SN54AS374, SN74ALS374A, SN74AS374 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS167B - APRIL 1982 - REVISED JULY 1996 I I • D-Type Flip-Flops in a Single Package With 3-State Bus Driving True Outputs | I • • Full Parallel Access for Loading

SN74AS162

Contextual Info: TEXAS INSTR LOGIC SSE 1> • flntl7a3'DDfl311S 2 SN54ALS160B THRU SN54ALS163B, SN54AS160 THRU SNS4AS163 SN74ALS160B THRU SN74ALS163B, SN74AS160 THRU SN74AS163 SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS D2661, APRIL 1982-REVISEO M A Y 1986 SN54ALS&#39;, S N 5 4 A S '. . . J PACKAGE

SN54ABT16646

Abstract: SN74ABT16646
Contextual Info: SN54ABT16646, SN74ABT16646 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS212A-JUNE 1992 - REVISED JULY 1994 Members of the Texas Instruments Wldebus Family State-of-the-Art EPfC-llB™ BiCMOS Design Significantly Reduces Power Dissipation

SN54HCT00

Abstract: SN74HCT00
Contextual Info: SN54HCT00, SN74HCT00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES S C LS 062A - NOVEMBER 1988 - REVISED JANUARY 1996 • Inputs Are TTL-Voltage Compatible • Package Options Include Plastic Small-Outline D , Thin Shrink Small-Outline (PW), and Ceramic Flat (W)

SN74ACT7811

Abstract: SN74ACT7881 SN74ACT7882
Contextual Info: SN74ACT7882 2048 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY S C A S 445A -JUN E 1 9 9 4 - REVISED DECEMBER 1996 Member of the Texas Instruments Widebus Family Input-Ready, Output-Ready, and Half-Full Flags Independent Asynchronous Inputs and Outputs Cascadable in Word Width and/or Word

pin diagram of 7804

Abstract: SN74ACT7804 SN74ACT7806 SN74ACT7814 SN74ALVC7804 SN74ALVC7806 SN74ALVC7814 vw64
Contextual Info: SN74ALVC7804, SN74ALVC7806, SN74ALVC7814 5 1 2 x 18, 2 5 6 x 1 8 , 6 4 x 18 FIRST-IN, FIRST-OUT MEMORIES S C AS 437-JU N E 1994 DL PACKAGE TOP VIEW RESET I 1 56 OE 55 Q 17 2 D 16 3 54 Q16 D 15 4 53 Q 15 D 14 5 52 GND D 13 6 51 Q 14 D12 7 50 D11 8 49 Vcc

AC08

Abstract: SN54AC08 SN74AC08
Contextual Info: SN54AC08, SN74AC08 QUADRUPLE 2-INPUT POSITIVE-AND GATES SCAS536 - SEPTEMBER 1995 EPIC Enhanced-Performance Implanted CMOS 1-jjm Process Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK) and

SN54ABT16240

Abstract: SN74ABT16240 54abt16240
Contextual Info: SN54ABT16240, SN74ABT16240 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS095B - DECEMBER 1991 - REVISED JULY 1994 SN54ABT16240. . . WD PACKAGE SN74ABT16240. . . DL PACKAGE TOP VIEW Members of the Texas Instruments Wldebus Family State-of-the-Art EPIC-UB™ BiCMOS Design

A20C

Abstract: A23C A25C A26C SN74ACT3622 SN74ACT3632 SN74ACT3642
Contextual Info: SN74ACT3642 1024x36x2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS440A - JUNE 1994 - REVISED SEPTEMBER 1995 Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Two Independent Clocked FIFOs Buffering Data in Opposite Directions Mailbox-Bypass Register for Each FIFO

SN74ABT533A

Abstract: SN54ABT533
Contextual Info: SN54ABT533, SN74ABT533A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS186C - JANUARY 1991 - REVISED JUNE 1996 • State-of-the-Art EPIC-UB BiCMOS Design Significantly Reduces Power Dissipation Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17

SN74LVC126A

Contextual Info: SN74LVC126A QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCAS339D - MARCH 1994 - REVISED JANUARY 1997 • • • • D, DB, OR PW PACKAGE TOP VIEW EPIC (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V