SN74ACT3642 Search Results

IC51-1324-828

Abstract: SN74ACT3622 SN74ACT3632 SN74ACT3642
Contextual Info: SN74ACT3642 1024 x 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS440A – JUNE 1994 – REVISED SEPTEMBER 1995 D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Two Independent Clocked FIFOs Buffering Data in Opposite Directions

A14C

Abstract: A15C A23C A25C SN74ACT3622 SN74ACT3632 SN74ACT3642
Contextual Info: SN74ACT3642 1024x36x2 CLOCKED FIRST-IN, FIRST-OUT MEMORY SC A S440-JUN E 1994 IRB, ORB, AEB, and AFB Flags Synchronized by CLKB Low-Power 0.8-Micron Advanced CMOS Technology Supports Clock Frequencies up to 67 MHz Free-Running CLKA and CLKB Can Be Asynchronous or Coincident

IC51-1324-828

Abstract: SN74ACT3622 SN74ACT3632 SN74ACT3642
Contextual Info: SN74ACT3642 1024 x 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS440B – JUNE 1994 – REVISED JULY 1997 D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Two Independent Clocked FIFOs Buffering Data in Opposite Directions

A20C

Abstract: A23C A25C A26C SN74ACT3622 SN74ACT3632 SN74ACT3642
Contextual Info: SN74ACT3642 1024x36x2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS440A - JUNE 1994 - REVISED SEPTEMBER 1995 Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Two Independent Clocked FIFOs Buffering Data in Opposite Directions Mailbox-Bypass Register for Each FIFO

TMS320C31

Abstract: SN74ABT3611 SN74ABT3612 SN74ACT3622 SN74ACT3632 SN74ACT3638 SN74ACT3641 SN74ACT3642 SN74ACT3651
Contextual Info: FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control Kam Kittrell and Steve Strom Advanced System Logic – Semiconductor Group SCAA007A March 1996 1 IMPORTANT NOTICE Texas Instruments TI reserves the right to make changes to its products or to discontinue any semiconductor

IC51-1324-828

Abstract: SN74ACT3622 SN74ACT3632 SN74ACT3642
Contextual Info: SN74ACT3632 512 x 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS224C – JUNE 1992 – REVISED SEPTEMBER 1995 D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Two Independent 512 × 36 Clocked FIFOs Buffering Data in Opposite Directions

ON B34

Abstract: SN74ACT3632 SN74ACT3642 IC51-1324-828 SN74ACT3622
Contextual Info: SN74ACT3632 512 x 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS224C – JUNE 1992 – REVISED SEPTEMBER 1995 D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Two Independent 512 × 36 Clocked FIFOs Buffering Data in Opposite Directions

A23C

Abstract: IC51-1324-828 SN74ACT3622 SN74ACT3632 SN74ACT3642
Contextual Info: SN74ACT3632 512 x 36 x 2 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS224A - JUNE 1992 - REVISED AUGUST 1993 • IRB, ORB, AEB, and AFB Flags Synchronized by CLKB * Low-Power 0.8-Micron Advanced CMOS Technology • Supports Clock Frequencies up to 67 MHz • Fast Access Times of 11 ns

A14C

Abstract: A15C IC51-1324-828 SN74ACT3622 SN74ACT3632 SN74ACT3642
Contextual Info: SN74ACT3622 256 x 36 x 2 CLOCKED FIRST-IN, FIRST-OUT MEMORY _ SCAS247A -A U G U S T 1993 - REVISED JUNE 1994 Free-Running CLKA and CLKB Can Be Asynchronous or Coincident IRB, ORB, AEB, and AFB Flags Synchronized by CLKB Two Independent Clocked FIFOs Buffering

Contextual Info: SN74ACT3622 256 x 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS247D – AUGUST 1993 – REVISED APRIL 1998 D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Two Independent Clocked FIFOs Buffering Data in Opposite Directions

Contextual Info: SN74ACT3632 512 x 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS224D – JUNE 1992 – REVISED APRIL 1998 D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Two Independent 512 × 36 Clocked FIFOs Buffering Data in Opposite Directions

transistor w2d

Abstract: transistor W1A 78 R-PDSO-G16 Package transistor w1d f 7914 b texas transistor w2a wirebond die flag lead frame CPU 414-2 Processor Module DATASHEET OF 8 pin DIP IC 741 transmitter tube 807
Contextual Info: HighĆPerformance FIFO Memories European Edition Designer’s Handbook 1995 Advanced System Logic Printed in U.S.A. 0195 – CP SCAA024 Designer’s Handbook HighĆPerformance FIFO Memories European Edition 1995 HighĆPerformance FIFO Memories European Edition

IC51-1324-828

Abstract: SN74ACT3622 SN74ACT3632 SN74ACT3642
Contextual Info: SN74ACT3622 256 x 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS247C – AUGUST 1993 – REVISED SEPTEMBER 1995 D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Two Independent Clocked FIFOs Buffering Data in Opposite Directions

SN74ALVCH162245

Abstract: Schottky Barrier Diode Bus-Termination Array SN7400 CLOCKED SLLS210 SCAD001D TEXAS INSTRUMENTS SN7400 SERIES buffer SN74LVCC4245 sn74154 SDAD001C SN7497
Contextual Info: Section 4 Logic Selection Guide ABT – Advanced BiCMOS Technology . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3 ABTE/ETL – Advanced BiCMOS Technology/ Enhanced Transceiver Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9

Contextual Info: SN74ACT3622 256 x 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS247D – AUGUST 1993 – REVISED APRIL 1998 D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Two Independent Clocked FIFOs Buffering Data in Opposite Directions

Contextual Info: SN74ACT3632 512 x 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS224D – JUNE 1992 – REVISED APRIL 1998 D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Two Independent 512 × 36 Clocked FIFOs Buffering Data in Opposite Directions

IC51-1324-828

Abstract: SN74ACT3622 SN74ACT3632 SN74ACT3642
Contextual Info: SN74ACT3622 256 x 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS247C – AUGUST 1993 – REVISED SEPTEMBER 1995 D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Two Independent Clocked FIFOs Buffering Data in Opposite Directions

IC51-1324-828

Abstract: SN74ACT3622 SN74ACT3632 SN74ACT3642
Contextual Info: SN74ACT3622 256 x 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS247D – AUGUST 1993 – REVISED APRIL 1998 D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Two Independent Clocked FIFOs Buffering Data in Opposite Directions

Contextual Info: SN74ACT3622 256 x 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS247D – AUGUST 1993 – REVISED APRIL 1998 D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Two Independent Clocked FIFOs Buffering Data in Opposite Directions

120-pin, microprocessor

Contextual Info: PRODUCT OVERVIEW FIFO PRODUCT OFFERINGS Advanced Application-Specific Clocked FIFOs D EV IC E ORGANIZATION SP EED SORT tc "8 MAXIMUM FREQUENCY (MHz) ACCESS TIME (ns) PACKAQE PITCH (mm) AREA (mm2) 165 SN74ACT2226 SN74ACT2228 64 X 1 256 X 1 22 20 8/16 24-pin SO IC (DW)

Contextual Info: SN74ACT3632 512 x 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS224D – JUNE 1992 – REVISED APRIL 1998 D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Two Independent 512 × 36 Clocked FIFOs Buffering Data in Opposite Directions

sk2 354

Abstract: A12C A14C A15C A25C SN74ACT3622 SN74ACT3632 SN74ACT3642
Contextual Info: SN74ACT3632 512x36x2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS224C - JUNE 1992 - REVISED SEPTEMBER 1995 Free-Running CLKA and CLKB Can Be Asynchronous or Coincident • IRB, ORB, AEB, and AFB Flags Synchronized by CLKB Two Independent 512 x 36 Clocked FIFOs

IC51-1324-828

Abstract: SN74ACT3622 SN74ACT3632 SN74ACT3642
Contextual Info: SN74ACT3632 512 x 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS224D – JUNE 1992 – REVISED APRIL 1998 D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Two Independent 512 × 36 Clocked FIFOs Buffering Data in Opposite Directions

IC51-1324-828

Abstract: SN74ACT3622 SN74ACT3632 SN74ACT3642
Contextual Info: SN74ACT3622 256 x 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS247D – AUGUST 1993 – REVISED APRIL 1998 D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Two Independent Clocked FIFOs Buffering Data in Opposite Directions