A8A12 Search Results

FNR10

Abstract: B158-H6987-X-X-7600 a64 marking code
Contextual Info: SIEMENS C540U/C541U Data Sheet Revision History : 1997-10-01 Previous Releases none Original Version Page / Chapters Subjects (changes since last revision) Edition 1997-10-01 Published by Siemens AG, Bereich Ha lb le iter, MarketingKommunikation, BalanstraBe 73,

Contextual Info: SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025B - AUGUST 1998 - REVISED JUNE 2002 D Single-Chip Parallel Multiple D D D D D D D D D D D D Instruction/Multiple Data MIMD Digital Signal Processor (DSP) More Than Two Billion RISC-Equivalent Operations per Second

Contextual Info: SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025B - AUGUST 1998 - REVISED JUNE 2002 D Single-Chip Parallel Multiple D D D D D D D D D D D D Instruction/Multiple Data MIMD Digital Signal Processor (DSP) More Than Two Billion RISC-Equivalent Operations per Second

MC146805E2P

Abstract: 00FF CDP6805E2CE IA6805E2 IA6805E2-PDW40I IA6805E2-PLC44I MC146805E2 MC146805E2CP M3839
Contextual Info: IA6805E2 Microprocessor Unit Data Sheet As of Production Version 00 FEATURES • • • • • • • • • • • Form, Fit, and Function Compatible with the Harris  CDP6805E2CE and Motorola  MC146805E2 Internal 8-bit Timer with 7-Bit Programmable Prescaler

RCA15

Abstract: 0x01000800 NTH44
Contextual Info: TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 — APRIL 1998 • • • • • GGP PACKAGE BOTTOM VIEW Single Chip Parallel MIMD DSP Over 1.5 Billion RISC-like Operations per Second Master Processor (MP) − 32-Bit RISC Processor − IEEE-754 Floating Point

Contextual Info: SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025B - AUGUST 1998 - REVISED JUNE 2002 D Single-Chip Parallel Multiple D D D D D D D D D D D D Instruction/Multiple Data MIMD Digital Signal Processor (DSP) More Than Two Billion RISC-Equivalent Operations per Second

P87C575EHAA I

Abstract: P83C575EHPN 80C51 80C575 83C575 87C575 EC20D 2031h
Contextual Info: Philips Semiconductora Microcontroller Product 7 1 1 □ fl 2 b 0□bbb03 CMOS single-chip 8-bit microcontroller Product specification PHIN 80C575/83C575/87C575 • 80C51 based architecture - 8k x 8 ROM 83C575) - 8k x 8 EPROM (87C575) - ROMIess (80C575)

siemens 8032 cpu

Abstract: siemens 8032 SIEMENS 80515 80535 80515 88H1 MC 80535 Microcontroller Family SAB 8051 Pocket Guide 80515 application 80515/80535 8 Bit Microcontroller
Contextual Info: SIEM EN S High-Performance 8-Bit Single Chip Microcontroller SAB 80515/80535 P relim in ary SA B 80515 SAB 80535 • • • • • • • • • • • • • • • • • Microcontroller with factory mask-programmable ROM Microcontroller for external ROM

QP7C261-25LI

Abstract: GDFP2-F24 5962-9080307MJA QP7C261 CQCC1-N28 QP7C261-35QMB 5962-9080306MLA QP7C263-25JC QP7C264 QP7C261-25WMB
Contextual Info: QP7C261 / QP7C263 / QP7C264 May 4, 2011 8K x 8 Power-Switched and Reprogrammable PROM Features • 5V ±10% VCC, commercial, industrial and military • Windowed Packages available for reprogrammability • OTP One-Time-Programmable Packages available • High speed

TDA 9345

Abstract: EF9345P IC 74ls74 execution table 3 TDA RGB tv philips TGS0 tda 8035 EF9345 IC 74LS74 datasheet AM11 AM12
Contextual Info: EF9345 HMOS2 SINGLE CHIP SEMI-GRAPHIC DISPLAY PROCESSOR . . . . . . . . SINGLE CHIP LOW-COST COLOR CRT CONTROLLER TV STANDARD COMPATIBLE 50Hz or 60Hz 2 SCREEN FORMATS : - 25 (or 21) ROWS OF 40 CHARACTERS - 25 (or 21) ROWS OF 80 CHARACTERS ON-CHIP 128 ALPHANUMERIC AND 128

XG1010

Abstract: NT39 rs048
Contextual Info: TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 — APRIL 1998 GGP PACKAGE BOTTOM VIEW Single Chip Parallel MIMD DSP Over 1.5 Billion RISC-like Operations per Second . j AT AE AD AC AB M Y W V u T R P N M L K J H G F E D C 6 A Master Processor (MP) - 32-Bit RISC Processor

is46dr32801a-5bbla1

Abstract: 126-ball IS46DR32801A
Contextual Info: IS43DR32800A, IS43/46DR32801A 8Mx32 256Mb DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O SSTL_18-compatible • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS)

IS43DR83200A

Abstract: IS43DR16160A-3DBLI datasheet IS43DR16160A-37CBLI IS43DR83200A-37CBLI IS43DR32160A DDR2 x32
Contextual Info: IS43DR83200A IS43/46DR16160A, IS43DR32160A 32Mx8, 16Mx16, 16Mx32 stacked die DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle

HS-65643

Abstract: Harris Semiconductor, rad hard, HCS373 HCTS373 HS-65647RH
Contextual Info: Harris Semiconductor No. 9011 Military and Aerospace November 1994 SYNCHRONOUS OPERATION OF HARRIS RAD HARD SOS 64K ASYNCHRONOUS SRAMs Author: Steve Rivet E OR E1 The HCS373 and HCTS373 are both fabricated with SOS technology; each circuit is available hardened to 200K RADs

AUTOMATIC light dim dip CONTROLLER

Contextual Info: CMOS ST-BUS FAMILY MT9079 Advanced Controller for E1  Features • • • • • • • • • ISSUE 5 Meets applicable requirements of CCITT G.704, G.706, G.732, G.775, G.796, I.431 and ETSI ETS 300 011 HDB3, RZ, NRZ fibre interface and bipolar

74LS04C

Abstract: gd5f 80515K m8ab
Contextual Info: 47E D • fl23SfciüS D02ÔS7D fl ■ SIEG SIEMENS AKT IENGESELLSCHAF Xsrv SAB 80515K 8-Bit Single-Chip Microcontroller ROM-less Version • • • • • • • • • • • • • A dditional bus interface fo r external m em ory 256 x 8 RAM S ix 8-bit ports

MAX765x

Abstract: 8051 instruction set intel 8031 instruction set 8051 microcontroller code for measuring power factor 8051 timing diagram 74HC573 20 PIN 74HC573 Logic Package Information 8051 assembler intel 8051 opcode sheet power factor calculation by 8051 microcontroller
Contextual Info: Table of Contents 1. Introduction MAX765x Features …………………………… Performance Overview ………………………. Software Compatibility ………………………… 803x/805x Comparision ………………………. 2. MAX765x Architectural Overview

Contextual Info: TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 — APRIL 1998 • • • • • GGP PACKAGE BOTTOM VIEW Single Chip Parallel MIMD DSP Over 1.5 Billion RISC-like Operations per Second Master Processor (MP) − 32-Bit RISC Processor − IEEE-754 Floating Point

Contextual Info: IS43/46DR83200A IS43/46DR16160A 32Mx8, 16Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O SSTL_18-compatible • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS)

timing controller SHART

Abstract: T21N K4U52324Q SAMSUNG GDDR4 K4U52324QE-BC09 GDDR4
Contextual Info: 512M GDDR4 SGRAM K4U52324QE 512Mbit GDDR4 SGRAM 2M x 32Bit x 8 Banks Graphic Double Data Rate 4 Synchronous DRAM with Uni-directional Data Strobe and DLL 136Ball FBGA Revision 1.0 June 2006 INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

AT80C32X2

Abstract: AT80C52X2 VQFP44 footprint AT80C32X2-SLSUM 80C52 AT87C52X2 PDIL40 PLCC44 PQFP44 TS80C32X2
Contextual Info: Features • 80C52 Compatible • • • • • • • • • • • • • • • – 8051 Pin and Instruction Compatible – Four 8-bit I/O Ports – Three 16-bit Timer/Counters – 256 Bytes Scratchpad RAM High-speed Architecture 40 MHz at 5V, 30 MHz at 3V

MC146805E2P

Abstract: MC146805E2 MC146805E2CP 00FF CDP6805E2CE IA6805E2 IA6805E2-PDW40I IA6805E2-PLC44I
Contextual Info: IA6805E2 Microprocessor Unit Data Sheet As of Production Version 00 FEATURES • • • • • • • • • • • Form, Fit, and Function Compatible with the Harris  CDP6805E2CE and Motorola  MC146805E2 Internal 8-bit Timer with 7-Bit Programmable Prescaler

CDP1833C

Contextual Info: CMOS Peripherals. CDP1883, CDP1883C CLOCK- I MAO - 2 20 — vD0 19 -A0 MA I —— 3 18 -A9 MA2 - 4 17 - AIO 16 -All MA3 — 5 MA4 — 6 IS -AI 2 M A 5 - 7 M AS­ e 14 -CSÔ 13 — csT C È -v ss— 9 I tO -C"S2 II — CT3

HDS-200

Abstract: ADI991R2 TIL Display ADI991
Contextual Info: MOTOROLA SEM ICONDUCTOR TECHNICAL DATA Advance Information 8-Bit Microcomputers MC68HC05C4 MC68HSC05C4 MC68HC05C8 MC68HC805C4 This docum ent contains information on a new product. Specifications and information herein are subject to change w ithout notice.