A7 VC 23 Search Results

EDH411MN-10

Abstract: EDH411MN-12 EDH411MN-15
Contextual Info: Electronic Designs ln< - ' . EDH411MN-10/12/15 . < ^ ^ \ s v • -» •» V \ ' »v • PINOUTS VC C RASO DOUT A3 A6 □ IN WE RÂS1 AO A7 A8 C AS RAS2 c C C c c c C 8 c 9 c 17 C 18 C vc c vss • C om m on D IN /D O U T lines w ith separate RAS co ntro l

suss Instruments

Abstract: D3501 SN74ALS2238 gba 2674
Contextual Info: SN74ALS2238 32 x 9 x 2 ASYNCHRONOUS BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY D3501, APRIL 1990 N PACKAGE TOP VIEW Independent Asychronous Inputs and Outputs Bidirectional 30 R lT B DBF BO B1 B2 GND B3 B4 B5 B6 GND VCC 12 29 Vc c A7 A8 LDCKA FULLA UNCKB EMPTYB

Contextual Info: Very Low Power CMOS SRAM 256K X 8 bit BS62LV2006 Pb-Free and Green package materials are compliant to RoHS n FEATURES n DESCRIPTION Ÿ Wide VC C operation voltage : 2.4V ~ 5.5V Ÿ Very low power consumption : VCC = 3.0V Operation current : 23mA Max. 2mA (Max.)

Contextual Info: JHPD23C2000A 2,097,152-Bit Mask-Programmable CM OS ROM NEC NEC Electronics Inc. Description Pin Configuration Th e /¿PD 23C 2000A is a 2,097,152-bit ROM fabricated w ith C M O S siiicon-gate technology. This device is static in operation and can be organized as 131,072 w ords by

CD4016CN

Abstract: CD4016MW 10B3 CD4016C a7 P-CHANNEL cd4016cn datasheet CD4016CJ CD4016M CD4016MJ J14A
Contextual Info: CD4016M CD4016C Quad Bilateral Switch General Description The CD4016M CD4016C is a quad bilateral switch which utilizes P-channel and N-channel complementary MOS CMOS circuits to provide an extremely high ‘‘OFF’’ resistance and low ‘‘ON’’ resistance switch The switch will pass

Contextual Info: JUPD23C16000 16,777,216-Bit Mask-Programmable CMOS ROM NEC Electronics Inc. Pin Configuration Description T h e /JP D 23C 16000 is a w ith C M O S silic o n -g a te in o p e ra tio n an d has T T L -c o m p a tib le inputs 16,777,216-bit R O M fa b ric a te d

AHCT245

Abstract: SN54AHCT245 SN74AHCT245
Contextual Info: SN54AHCT245, SN74AHCT245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS S C LS 233E - O C TO BE R 1995 - R EVISED JU NE 1997 • EPIC Enhanced-Performance Implanted CMOS Process • High Latch-Up Immunity Exceeds 250 mA Per JESD 17 • • SN54AHC T245 . . . J OR W PACKAGE

Contextual Info: pPD23C4000A 4,194,304-Bit Mask-Programmable CMOS ROM NEC NEC Electronics Inc. Description Pin Configuration T h e /JP D 23C 4000A is a 4,194,304-bit ROM fa b ric a te d w ith C M O S silic o n -g a te technology. T h e d e v ic e is s ta tic in o p e ra tio n an d has th re e -s ta te o u tp uts, fu lly T T L c o m p a tib le in puts an d outp uts, an d an o u tp u t e n ab le

93479ADC

Abstract: 93479ADMQB 93479ALMQB 93479DC 93479DMQB 93479LMQB E28A J22A 96755
Contextual Info: 93479 ZWÄ National ÉüA Semiconductor 93479 256 x 9-Bit Static Random Access Memory General Description Features The 93479 is a 2304-bit read/write Random Access Memo­ ry RAM , organized as 256 words by nine bits per word. It is ideally suited for scratchpad, small buffer and other applica­

IR10D

Abstract: RPS_PRES HY514264 R1799-2 TPI-10 74f04d 980b bergstik ARB12 mst12
Contextual Info: LXD980/980B Reference Design Schematics Reference Design Schematics Reference Design Schematic, Sheet 1:LXD 980 Top Level Schematic
 D-1 LXD980/980B Reference Design Users Guide Reference Design Schematic, Sheet 2:Raptor1 1 2 IR10DAT IR10CLK IR10ENA IR10DEN

HC540A

Contextual Info: TOSHIBA TC74HCT54QAP/AF/AFW TC74HCT541AP/AF/AFW Octal Bus Buffer with TTL Input Level TC74HCT540A Inverting, 3-State Outputs TC74HCT541A Non-Inverting, 3-State Outputs The TC74HCT540A/TC74HCT541A are high speed CMOS OCTAL BUS BUFFERS fabricated with silicon gate C2MOS

Contextual Info: _ CSS3SS . High Performance 4 0 9 6 x 8 PROM TiW PROM Family 5 3 /6 3 S 3 2 8 1 5 3 /6 3 S 3 2 8 1 A Features/Benefits Description • 35-ns maximum access time The 53/63S3281 is a high-speed 4Kx8 PROM w hich uses industry standard pin out. • 32768-bit memory

Contextual Info: TOSHIBA TC74HC245AP/AF/AFW TC74HC640AP/AF Octal Bus Transceiver TC74HC245 3-State, Non-Inverting TC74HC640 3-State, Inverting The TC74HC245A, and 640A are high speed CMOS OCTAL BUS TRANSCEIVERS fabricated with silicon gate C2MOS technology. They achieve the high speed operation similar to equivalent

HARRIS 7621

Abstract: 7621 HM-76161 HM-76160 HM-7620 HM-7621 hm7621a
Contextual Info: fW ì H M -7620/21 HARRIS S E M IC O N D U C T O R P R O D U C T S D IV IS I O N A DIVISION or 512 x 4 P R O M H A R RIS CORPO RATION H M -7 6 2 0 — Open Collector Outputs HM-7621 — "Three State" Outputs Pinouts Features • 70ns M A X IM U M A D D R E S S ACCESS T IM E

23c256

Contextual Info: HUALON MICROELECTRONICS 24E D 45^8041 0 0 0 D0 SD s • ~V-Lllp~l'd>'-}C S HM23C256/A 32K x 8 MASK ROM Features * * * * * * * * Three-state outputs. * 23C256 — Non power down version. _ — Two programmable chip selects CS . * 23C256A _ — Automatic power down (CE).

Contextual Info: DUAL 8-INPUT MULTIPLEXER | Î J S ï l i l l SYNERGY SEMICONDUCTOR PRELIMINARY DESCRIPTION FEATURES The SY100/101S363 is a dual 8-input multiplexer, designed fo use in new, high performance EC L systems. The three Data Select inputs So, S t, S 2 determine the bits from each of the 8 inputs (An,

AmZ8103

Abstract: AmZ8104 AMZ8104DC
Contextual Info: AmZ8103 • AmZ8104 Octal Three-State Bidirectional Bus Transceivers DISTINCTIVE CHARACTERISTICS FUNCTIONAL DESCRIPTION • 8-bit bidirectional data flow reduces system package count • 3-state inputs/outputs for interfacing with bus-oriented systems PNP inputs reduce input loading

82S212

Abstract: N82S212 N82S212F S82S212 S82S212F
Contextual Info: BIPOLAR MEMORY DIVISION MAY 1982 2304-BIT BIPOLAR RAM 256 X 9 DESCRIPTION The o rg a n iza tio n o f th e 82S212 a llo w s b yte w id e sto ra g e o f data, in c lu d in g parity. W here p a rity is n ot required, th e n in th b it can be used as a tag fo r each w ord sto re d .

Contextual Info: PI3VT32X245

Contextual Info: 2048x8 Registered PROM 5 3 /6 3 R A 1 6 8 1 5 3 /6 3 R A 1 6 8 1 A ^ j w ith Asynchronous Enable Features/ Benefits Description • Synchronous output enable The 53/63RA1681 and 53/63RA1681A are 2Kx8 PROMs with on-chip “ D''-type registers. O utput enable control through an

128x128

Abstract: 63S1641 53S1641 53S1641A 63S1641A
Contextual Info: High Performance 4096x4 PROM TiW PROM Fam ily 53/63S1641 53/63S1641A Features/Benefits Description • 35-ns maximum access time The 53/63S1641 features low input current PNP inputs, full Schottky clamping and three-state outputs. The titaniumtungsten fuses store a logical low and are programmed to the

s6665

Contextual Info: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT 64M-BIT VIRTUAL CHANNEL SDRAM with DOUBLE DATA RATE 64M-BIT VIRTUAL CHANNEL SDRAM VERSION 0.1 Description The 64 M-bit Virtual Channel VC SDRAM is implemented to be 100% pin and package com patible to the industry

27C010L

Abstract: M27C010
Contextual Info: R C H PRELIMINARY I I - P January 1998 S E M I C O N D U C T O R -n FM 27C 010-L 1,048,576-B it 128K x 8 Low Pow er Fast EPROM General Description The FM 27C 010-L is a low -pow er 1 Mbit, 5V-only one-lim eprogram m able (OTP) read-only m em ory (EPROM ), orga­

63S1681

Abstract: monolithic memories 53S1681 63S1681A 2048x8 53S1681A Monolithic Memories PROM programming
Contextual Info: High Performance 2 0 4 8 x 8 PROM TiW PROM Fam ily 53 /63S 1681 5 3 /6 3 S 1 6 8 1 A Features/Benefits Description • 35-ns maximum access time The 53/63S1681 is a high-speed 2Kx8 PROM which uses industry standard package and pin out. In addition, the device is