KBYTE Search Results

TSB12LV41

Contextual Info: DATA TRANSMISSION C o n s u m e r Electronics G o Digital w ith N e w Link-Layer Controllers he TSB12LV41 for MPEG2/DSS receiving IEEE 1394 packets simulta­ and the TSB12LV42 for digital neously. A separate, implemented video data streams are TTs latest 8-Kbyte FIFO, accessible via the BDIF,

Part Marking STMicroelectronics TSSOP8

Abstract: M95256
Contextual Info: M95256-W M95256-R M95256-DR M95256-DF 256-Kbit serial SPI bus EEPROM with high-speed clock Datasheet − production data Features • Compatible with the Serial Peripheral Interface SPI bus ■ Memory array – 256 Kb (32 Kbytes) of EEPROM – Page size: 64 bytes

ISO 18092

Abstract: 78CLFX2406P ISO-14443A SLE78CLFX2406P M7892 78CLF 78CLFX
Contextual Info: SLE 78CLFX2406P M SOLID FLASH 16-bit Security Controller with “Integrity Guard” Optimized for Contactless and Dual-Interface Payment Applications in 90 nm CMOS Technology 240 kBytes SOLID FLASH™ 6 kBytes RAM Sho rt Pro duct O ve r vie w July 2012

SLE 77CFX1840P

Abstract: M7793 77CFX1840P
Contextual Info: SLE 77CFX1840P M7793 16-bit Flash Security Controller Optimized for Midrange Payment Applications in 90 nm CMOS Technology 184 KBytes SOLID FLASH 6 KBytes RAM Crypto@2304T Engine with Register Lengths of up to 2304 Bits, Certified RSA and ECC Libraries

m7793

Abstract: RSA 4096bit 90 nm CMOS 2304T
Contextual Info: SLE 77CFX1560P M7793 16-bit Flash Security Controller Optimized for Midrange Payment Applications in 90 nm CMOS Technology 156 KBytes SOLID FLASH 6 KBytes RAM Crypto@2304T Engine with Register Lengths of up to 2304 Bits, Certified RSA and ECC Libraries

76CF5120P

Abstract: SLM76CF5120P p-m2m5.1 76CF
Contextual Info: SLM 76CF5120P 504 kBytes Solid FlashTM 12 kBytes RAM 16-bit Flash security controller optimized for “industrial” M2M applications in 0.13 µm CMOS technology Sho rt Pro duc t O ve r vi e w May 2011 Chi p C ard & Sec u ri t y SLM 76CF5120P SLM 76CF5120P Short Product Overview

66C367PE

Contextual Info: SLE 66C367PE 8/16-Bit Security Controller with enhanced instruction set for large memories in 0.22 µm CMOS Technology 196-Kbytes ROM,4352 bytes RAM, 36-Kbytes EEPROM Dual Key Triple DES Sho rt Pro duc t O ve r vi e w May 2011 Chi p C ard & Sec u ri t y SLE 66C367PE

AT91SAM3U4

Abstract: at91sam3 1N1308 MAR 735 REGULATOR IC 7912 pin identify AT91SAM3U4E SAM3u1 AT91SAM3U 3961 G.E 0x20180
Contextual Info: Features • Core • • • • • • – ARM Cortex®-M3 revision 2.0 running at up to 96 MHz – Memory Protection Unit MPU – Thumb®-2 instruction set Memories – From 64 to 256 Kbytes embedded Flash, 128-bit wide access, memory accelerator,

6206a

Abstract: K-Line transceiver w1p 84 st10f2xx sigma asc 333 24 pin K-line ST10F276E W1P 59 st10 Bootstrap st10273e
Contextual Info: ST10F276E 16-bit MCU with MAC unit 832 Kbyte Flash memory and 68 Kbyte RAM Datasheet − production data Features • ■ ■ ■ ■ ■ Highly performance 16-bit CPU with DSP functions – 31.25ns instruction cycle time at 64MHz max CPU clock – Multiply/accumulate unit MAC 16 x 16-bit

Contextual Info: FEDL610Q793-01 Issue Date: 6/12/2013 ML610Q793 8-bit Microcontroller for Sensor Control • General Description The ML610Q793 is a high-performance 8-bit low power microcontroller optimized for sensor hub, that integrates LAPIS Semiconductor’s original high-performance 8-bit CPU core with a 16-bit multiplier/divider co-processor, 64 kByte flash

M95M01-D

Abstract: M95M01-DF marking M95 m01d
Contextual Info: M95M01-DF M95M01-R 1-Mbit serial SPI bus EEPROM Datasheet − production data Features • Compatible with the Serial Peripheral Interface SPI bus ■ Memory array – 1 Mb (128 Kbytes) of EEPROM – Page size: 256 bytes SO8 (MN) 150 mil width ■ Write

m955

Abstract: M9551 M95512-DF
Contextual Info: M95512-W M95512-R M95512-DR M95512-DF 512-Kbit serial SPI bus EEPROM Datasheet − production data Features • Compatible with the Serial Peripheral Interface SPI bus ■ Memory array – 512 Kb (64 Kbytes) of EEPROM – Page size: 128 bytes SO8 (MN) 150 mil width

STM32F051

Abstract: STM32F051R8 RM0091 STM32F0 STM32 IWDG STM32F051x STM32F051K STM32F051R stm32f05 STM32F051C8
Contextual Info: STM32F051x4 STM32F051x6 STM32F051x8 Low- and medium-density advanced ARM -based 32-bit MCU with 16 to 64 Kbytes Flash, timers, ADC, DAC and comm. interfaces Datasheet − production data Features • Core: ARM 32-bit Cortex™-M0 CPU, frequency up to 48 MHz

atmel 324

Abstract: ARM926EJ-S AT91SAM ISO7816 SAM9G45 AT91SAM9G45B-CU UHP4 ddr2 16bit NAND Flash controller ecc DFSDM
Contextual Info: Features • 400 MHz ARM926EJ-S ARM Thumb® Processor – 32 KBytes Data Cache, 32 KBytes Instruction Cache, MMU • Memories • • • • – DDR2 Controller 4-bank DDR2/LPDDR, SDRAM/LPSDR – External Bus Interface supporting 4-bank DDR2/LPDDR, SDRAM/LPSDR, Static

AM29030

Abstract: MiniMON29K CERQUAD AM29035 CGY145 GQD144 ID31 Am29202 am29000 AM29030-25GC
Contextual Info: AMENDMENT Am29030 and Am29035  RISC Microprocessors with 8-Kbyte/4-Kbyte Instruction Cache Advanced Micro Devices This amendment adds preliminary information on switching characteristics over commercial operating ranges for the 25-MHz Am29030 microprocessor.

iso7816 sim

Abstract: C251 e purse 80C51 ISO7816-3 T89SC256C smart card
Contextual Info: T89SC256C C 2 5 1 8 / 1 6 - b i t C r y p t o c o n t r o l l e r Key Features The T89SC256C is a 8/16-bit secure cryptocontroller ❶ 256 Kbytes on-chip Flash Memory ❶ 4.5 Kbytes on-chip RAM ❶✶ C251 core high frequency ❶ Arithmetic Crypto Processor

STV9425

Abstract: transistor ZY SDIP24 STV9425B STV9426
Contextual Info: STV9425 - STV9425B STV9426 MULTISYNC ON-SCREEN DISPLAY FOR MONITOR . . . . . . . . . . PRELIMINARY DATA CMOS SINGLE CHIP OSD FOR MONITOR BUILT IN 1 KBYTE RAM HOLDING : - PAGES’DESCRIPTORS - CHARACTER CODES - USER DEFINABLE CHARACTERS 128 ALPHANUMERIC CHARACTERS OR

F844

Abstract: Static Random Access Memory SRAM F848 power transistor array F840 F84A F852 MC68377 memory sram
Contextual Info: SECTION 12 STATIC RANDOM ACCESS MEMORY SRAM 12.1 Introduction This SRAM module is a fast access (two clocks) general purpose 8 Kbytes (8,192 bytes) static RAM (SRAM) for the MCU and is accessed via the IMB3. In addition there is 2 Kbytes (configured as four blocks of 512 bytes each) of patch static RAM. These

kl2 t1 transistor

Abstract: KYOCERA KBR
Contextual Info: Ordering number: EN3653B _ CMOS LSI LC65102A, LC65104A 4-bit Single-chip Microprocessors :'S s. •Á V // / ^ / / / / .f A' '^ O - -iK \ ’V OVERVIEW / / 0 ' " A- The LC65102A and LC65104A are 4-bit, single-chip microprocessors that incorporate 2 Kbyte RO M and

Contextual Info: Freescale Semiconductor Data Sheet: Document Number: MSC8144E Rev. 10, 8/2008 MSC8144E FC-PBGA–783 29 mm x 29 mm Quad Core Digital Signal Processor • Four StarCore SC3400 DSP subsystems, each with an SC3400 DSP core, 16 Kbyte L1 instruction cache, 32 Kbyte L1 data cache,

Contextual Info: ST52T410/T420/ E420  ST52T410/T420/E420 8-BIT INTELLIGENT CONTROLLER UNIT ICU Three Timer/PWMs, ADC, WDG Memories Up to 4 Kbytes OTP 128 bytes of RAM Readout Protection Core Register File Based Architecture 55 instructions Hardware multiplication and division

KU80486SX

Abstract: 240486 KU80486SXSA33 ku80486 272769 240950 A80486SXSA33 SL ENHANCED I486 D1542 a80486sx
Contextual Info: Embedded Intel486 SX Processor Datasheet Product Features • ■ ■ ■ ■ 32-Bit RISC Technology Core 8-Kbyte Write-Through Cache Four Internal Write Buffers Burst Bus Cycles Dynamic Bus Sizing for 8- and 16-bit Data Bus Devices SL Technology ■ ■

USER S MANUAL oki 32 lcd tv

Abstract: USER MANUAL oki 42 lcd tv USER S MANUAL oki 22 lcd tv MSM64155A MSM64P155 QFP100-P-1420-BK USER MANUAL oki 22 lcd tv
Contextual Info: O K I Semiconductor MSM64155A/64155AL Built-in M elody C ircu it and L C D D river 4-Bit M icrocontroller GEN ERAL DESCRIPTION The MSM64155A 1.5 V /64155A L (3.0 V) is a 4-bit microcontroller that incorporates an n X -4/ 20 CPU core. The MSM64155A fam ily offers a built-in 256-nibble data m em ory, 4-Kbyte program

DFSDM

Abstract: SAM9M10 K 2141 AC97 ARM926EJ-S AT91SAM ISO7816 NBC 3111 hc 541 rfid reader id-20
Contextual Info: Features • 400 MHz ARM926EJ-S ARM Thumb® Processor – 32 KBytes Data Cache, 32 KBytes Instruction Cache, MMU • Memories • • • • – DDR2 Controller 4-bank DDR2/LPDDR, SDR/LPSDR – External Bus Interface supporting 4-bank DDR2/LPDDR, SDR/LPSDR, Static