A1XB Search Results

HAI 7203

Abstract: ACT8847 74ACT8847 SN74 multiplier
Contextual Info: TEXAS INSTR LOGIC SSE D 0^1723 GQÖS7G3 7 SN74ACT8847 64-Bit Floating Point Unit • Meets IEEE Standard for Single- and DoublePrecision Formats • Performs Floating Point and Integer Add, Subtract, Multiply, Divide, Square Root, and Compare • 64-Bit IEEE Divide in 11 Cycles, 64-Bit Square

Contextual Info: DM54L51/DM74L51 National Semiconductor DM54L51/DM74L51 Dual 2-Wide 2-Input, 2-Wide 3-Input AND-OR-INVERT Gates General Description Absolute Maximum Ratings Note d T h is d e v ic e c o n ta in s tw o c o m b in a tio n s o f g a te s e a ch o f w h ic h p e rfo rm s th e lo g ic A N D -O R -IN V E R T fu n c tio n .

lu2b

Abstract: TESYS U LU2B 12BL a6xb N11L LUCB1XBL LUCM05BL 32BL LU2B12 LULC09
Contextual Info: Presentation 1 TeSys motor starters - open version TeSys U starter-controllers DeviceNet communication module and pre-wired coil connection components 567225 1 2 Presentation 3 When used in conjunction with the power base and control unit, communication module LUL C09 allows TeSys U starter-controllers and controllers to be controlled

AP-812

Abstract: AP812 Intel application note SIMD
Contextual Info: AP-812 Applying Streaming SIMD Extensions to Collision Detection Applying Streaming SIMD Extensions to Collision Detection Version 1.1 01/99 Order Number: 243646-002 02/04/99 AP-812 Applying Streaming SIMD Extensions to Collision Detection Information in this document is provided in connection with Intel products. No license, express or

A1XB

Abstract: DM54 DM74 A2XB
Contextual Info: DM54L51/DM74L51 National Semiconductor DM54L51/DM74L51 Dual 2-Wide 2-Input, 2-Wide 3-Input AND-OR-INVERT Gates General Description Absolute Maximum Ratings Note d T h is d e v ic e c o n ta in s tw o c o m b in a tio n s o f g a te s e a ch o f w h ic h p e rfo rm s th e lo g ic A N D -O R -IN V E R T fu n c tio n .

thyristor tag 8422

Abstract: ditty EPC-31 gpr 163 MIPS R4000 mmi2 thyristor handbook transistor mfsa 42 C790 D-10
Contextual Info: TX System RISC TX79 Core Architecture Symmetric 2-way superscalar 64-bit CPU Rev. 2.0 The information contained herein is subject to change without notice. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or

matlab programs for impulse noise removal

Abstract: verilog code for cordic algorithm for wireless verilog code for CORDIC to generate sine wave block interleaver in modelsim matlab programs for impulse noise removal in image vhdl code for cordic matlab programs for impulse noise removal in imag vhdl code to generate sine wave PLDS DVD V9 CORDIC to generate sine wave fpga
Contextual Info: DSP Builder Handbook Volume 1: Introduction to DSP Builder 101 Innovation Drive San Jose, CA 95134 www.altera.com HB_DSPB_INTRO-1.0 Document Version: Document Date: 1.0 July 2010 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other

Cyclone II DE2 Board DSP Builder

Abstract: verilog code for cordic algorithm for wireless la vhdl code for a updown counter verilog code for CORDIC to generate sine wave verilog code for cordic algorithm for wireless simulink matlab PFC 4-bit AHDL adder subtractor simulink model CORDIC to generate sine wave fpga vhdl code for cordic
Contextual Info: DSP Builder Handbook Volume 2: DSP Builder Standard Blockset 101 Innovation Drive San Jose, CA 95134 www.altera.com HB_DSPB_STD-1.0 Document Version: Document Date: 1.0 June 2010 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other