32BL Search Results

BTL-32BLC-XX-X

Contextual Info: MEGA BRIGHT LED BTL-32BLC-XX-X Package Dimension Product Features Ultra Bright Blue Color High Light Output 3mm Diameter Circular Package Water Clear Lens Highly Reliable IC Compatible Leads without Stand Off Applications Automotive Front Panel Indicator Special Lighting

IMSG176/8

Contextual Info: TVP3027 VIDEO INTERFACE PALETTE XLAS106-MAY 1995 • Direct Interfacing to Video RAM • Supports Color Depths of 4-, 8-, 16-, 24-, and 32-Blt/Plxel • 64-Bit-Wide Pixel Bus • Supports Overscan For Creation of Custom Screen Borders • Color-Keyed Switching of Direct Color and

Contextual Info: TVP3026 VIDEO INTERFACE PALETTE X L A S 0 9 8 A - MAY 1995 | • Supports System Resolutions up to 1600 x 1280 at 76-Hz Refresh Rate • Versatile Pixel Bus Interface Supports Little- and Big-Endian Data Formats • Supports Color Depths of 4-, 8-, 16-, 24-,

Contextual Info: SN54AHC138, SN74AHC138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS S CLS258C - DECEM BER 1995 - REVISED JULY 1996 Operating Range 2-V to 5.5-V Vqc E P IC * Enhanced-Performance Implanted CMOS Process SN54AMC138 . . . J O R W PACKAGE SN74AHC138 . . . D, DB, N, OR PW PACKAGE

MX25L1635D

Abstract: MX25L163 mx25l1635 MX25L1635DM MX25L1635DM2I-12G mx25l1 MX25L1635DM2I IN3064 MX25L1605D mx25
Contextual Info: MX25L1635D MX25L1635D DATASHEET P/N: PM1374 1 REV. 1.5, OCT. 01, 2008 MX25L1635D Contents FEATURES . 5

Contextual Info: MX25L6475E MX25L6475E HIGH PERFORMANCE SERIAL FLASH SPECIFICATION P/N: PM1831 1 REV. 1.1, NOV. 11, 2013 MX25L6475E Contents 1. FEATURES. 4

Contextual Info: MX25L1673E MX25L1673E HIGH PERFORMANCE SERIAL FLASH SPECIFICATION P/N: PM1912 1 REV. 1.2, JAN. 14, 2014 MX25L1673E Contents 1. FEATURES. 4

8087 data types

Abstract: 8087 coprocessor instruction set 8087 coprocessor architecture bcd addition program of 8086 intel 8087 architecture coprocessor intel 8087 amd 8086 8087 architecture and configuration 8284A clock generator driver 8086 interfacing of memory devices with 8086
Contextual Info: 8087 Numeric Data Coprocessor ÌAPX86 Family DISTINCTIVE CHARACTERISTICS • • • High perform ance arithm etic and transcendental fu n c­ tions in hardware Supports 8-, 16-, 32-, 64-bit integer Performs 32-, 64-, 80-bit floating point calculations conforming to !EEE standard

IN3064

Abstract: MX25L3225D
Contextual Info: MX25L3225D MX25L3225D DATASHEET P/N: PM1432 1 REV. 0.00, SEP. 19, 2008 MX25L3225D Contents FEATURES . 5

Contextual Info: 32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT FEATURES: IDT49C460 IDT49C460A IDT49C460B IDT49C460C IDT49C460D IDT49C460E DESCRIPTION: • Fast Detect 10ns max. 12ns (max.) 16ns (max.) 25ns (max.) 30ns (max.) 40ns (max.) Correct 14ns (max.) 18ns (max.)

Contextual Info: w W 16-BIT CM O S ERROR DETECTION AND CO RRECTIO N UNIT IDT39C60A IDT ^ C6/2“ 1 IDT39C60 Inte3 rated Device Technology. Inc. MICROSLICE PRODUCT FEATURES: DESCRIPTION: • The IDT39C60 fam ily are high-speed, low-power, 16-bit Error De­ tection and Correction Units which generate check bits on a 16-bit

Contextual Info: ¡n tg l. 82596CA HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR • Performs Complete CSMA/CD Medium Access Control MAC Functions— Independently of CPU — IEEE 802.3 (EOC) Frame Delimiting — HDLC Frame Delimiting ■ Supports Industry Standard LANs

CD 2399 GP

Abstract: 80387 DX Users Manual Programmers Reference
Contextual Info: PRByBJOODOÂIfflr in t e i Intel486 DX MICROPROCESSOR 168-Pin Grid Array Package High Performance Design — RISC Integer Core with Frequent Instructions Executing in One Clock — 25 MHz, 33 MHz, and 50 MHz Clock — 80, 106, 160 Mbyte/sec Burst Bus — CHMOS IV and CHMOS V Process

coprocessor

Contextual Info: in y Intel387 SX MATH COPROCESSOR N e w A u to m a tic P o w e r M a n a g e m e n t — L o w P o w e r C o n su m p tio n — T y p ic a lly 100 m A in D y n a m ic M o de, an d 4 m A in Id le M o d e S o c k e t C o m p a tib le w ith In te l3 8 7 Fam ily

Contextual Info: in te i 386 DX MICROPROCESSOR HIGH PERFORMANCE 32-BIT CHMOS MICROPROCESSOR WITH INTEGRATED MEMORY MANAGEMENT Optimized for System Performance — Pipelined Instruction Execution — On-Chip Address Translation Caches — 20, 25 and 33 MHz Clock — 40, 50 and 66 Megabytes/Sec Bus

Contextual Info: 32-BIT AND 64-BIT IEEE FLOATING-POINT MULTIPLIER AND ALU DESCRIPTION: FEATURES: T h e IDT721264 flo a tin g -p o in t m u ltip lie r and the IDT721265 flo a tin g -p o in t ALU p ro v id e h ig l^ p e e d 3 2-b it and 64-bit flo a tin g ­ p o in t p ro c e s s in g ca p a b ility .

Contextual Info: IME D INTEGRATED DEVICE • 4Ö2S771 0003^22 1 ■ 16-BIT CMOS ERROR DETECTION AND CORRECTION UNIT MICROSLICE PRODUCT FEATURES: • • ■ T -¥ £ -/7 Pin-compatible to all versions of the 2960 • Military product available compliant to MIL-STD-883, Class B

008 cow 734

Contextual Info: 80960CF-33, -25, -16 32-BIT HIGH PERFORMANCE SUPERSCALAR PROCESSOR • Socket and Object Code Compatible with 80960CA • Two Instructions/Clock Sustained Execution • Four 59 Mbytes/s DMA Channels with Data Chaining • Demultiplexed 3'2-bit Burst Bus with Pipelining

Contextual Info: intJ 80C187 80-BIT MATH COPROCESSOR • High Performance 80-Bit Internal Architecture ■ Implements ANSI/IEEE Standard 7541985 for Binary Floating-Point Arithmetic ■ Upward Object-Code Compatible from 8087 ■ Fully Compatible with 387DX and 387SX Math Coprocessors. Implements all 387

Contextual Info: HYM •HYUNDAI 1M X 532100A M-Series 32-blt CMOS DRAM MODULE DESCRIPTION The HYM532100A is a 1M x 32-bit R e t page mode CMOS ORAM module consisting of eight HY514400A in 20/26 pin SOJ on a 72 pin glass-epoxy printed circuit board. 0.22nF decoupling capacitor is mounted lo r each DRAM.

Contextual Info: 80960CF-40 32-BIT HIGH-PERFORMANCE SUPERSCALAR PROCESSOR • Socket and Object Code Compatible with 80960CA • Two Instructions/Clock Sustained Execution • Four 71 Mbytes/s DMA Channels with Data Chaining • Demultiplexed 32-Bit Burst Bus with Pipelining

hall marking code A04

Abstract: INTELDX4 write-through YSS 928
Contextual Info: INTEL486 PROCESSOR FAMILY • lntelDX4TM P ro c e s s o r — Up to 100-MHz Operation -Speed-M ultiplying Technology — 32-Bit Architecture — 16K-Byte On-Chip Cache — Integrated Floating-Point Unit — 3.3V Core Operation with 5V Tolerant I/O Buffers

Contextual Info: HYUNDAI HYM532100A M-Series 1M x 32-blt CM O S DRAM MODULE DESCRIPTION The HYM532100A is a 1M x 32-bit Fast page mode CMO S DRAM module consisting of eight HY514400A in 20/26 pin SOJ on a 72 pin glass-epoxy printed circuit board. 0.2^uF decoupling capacitor is mounted for each DRAM.

Cyrix FasMath

Abstract: CX-83S87 cyrix 386SX fcom 7c DATA SHEET FOR OL 107 E SOLDER PEST FasMath 83D87 386SX CIRCUIT diagram 80386 83S87
Contextual Info: 83S87 User’s Manual High Performance CMOS Math Processor CYRIX CORP 3bE » H SSñ^ñn □ GQDlB'ì fi • T—49—1 2-05 FasMath CX-83S87 User's Manual January, 1990 o * P.O. Box 850118 Richardson, TX 76085-0118 CYR CYRIX CORP 3bE D ■ 2 5 ö t filici □ □ D D I M Q