A10A9 Search Results

lm814

Abstract: ID32-001
Contextual Info: TOSHIBA TC59LM814/06BFT-22,-24,-30 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 4,194,304-WORDSX4BANKSX16-BITS DOUBLE DATA RATE FAST CYCLE RAM 8,388,608-WORDSX4BANKSX8-BITS DOUBLE DATA RATE FAST CYCLE RAM DESCRIPTION TC59LM814/06BFT are a CMOS Double Data Rate Fast Cycle Random Access Memory DDR

Contextual Info: DS92LV1260 DS92LV1260 Six Channel 10 Bit BLVDS Deserializer Literature Number: SNLS134E DS92LV1260 Six Channel 10 Bit BLVDS Deserializer General Description Features The DS92LV1260 integrates six deserializer devices into a single chip. The chip uses a 0.25u CMOS process technology. The DS92LV1260 can simultaneously deserialize up to

S-29590A

Abstract: DIDO
Contextual Info: 目 次 特 長･････････････････････････････ 1 ピン配置図･････････････････････････ 1 端子説明･･･････････････････････････ 1

S590

Abstract: S-29530A S-29590A S-29590ADPA S-29630A S-29690A S-29690ADPA S-29X90A S690
Contextual Info: Contents Features. 1 Pin Assignment . 1 Pin Functions . 1 Block Diagram. 2

K4C560838C-TCB

Contextual Info: K4C5608/1638C 256Mb Network-DRAM Network-DRAM Specification Version 0.2 - 1 - REV. 0.2 Jan. 2002 K4C5608/1638C 256Mb Network-DRAM Revision History Version 0.0 Oct. / 5 / 2001 - First Release Version 0.1 (Dec. / 15 / 2001) - The product name is changed to Network-DRAM

Contextual Info: Nanya Technology Corp. DDR3 L 4Gb SDRAM NT5CB(C)512M8CN / NT5CB(C)256M16CP NT5CB(C)512M8CN / NT5CB(C)256M16CP Commercial, Industrial and Automotive DDR3(L) 4Gb SDRAM Features  Signal Integrity  JEDEC DDR3 Compliant - Configurable DS for system compatibility

SCANSTA11

Contextual Info: SCAN921260 X6 1:10 Deserializer with IEEE 1149.1 JTAG and at-speed BIST General Description Features The SCAN921260 integrates six deserializer devices into a single chip. The SCAN921260 can simultaneously deserialize up to six data streams that have been serialized by the

ZUA15

Abstract: ZUA12
Contextual Info: HM62W1400H Series 4194304-word x 1-bit High Speed CMOS Static RAM HITACHI ADE-203-773 Z Preliminary Rev. 0.0 Apr. 28, 1997 Description The HM62W1400H is an asyncronous high speed static RAM organized as 4-Mword x 1-bit. It has realized high speed access time (10/12/15 ns) with employing 0.35 (Am CMOS process and high speed circuit

Contextual Info: K4C89093AF Target 288Mb Network-DRAM-II Specification Version 0.2 - 1 - REV. 0.2 Aug. 2003 K4C89093AF Target Revision History Version 0.0 Nov. 2002 - First Release Version 0.1 (Apr. 2003) - Added 800Mbps(400Mhz) product - Changed operating temperature from Ta to Tc.

Contextual Info: K4C89183AF 288Mb Network-DRAM-II Specification Version 0.11 - 1 - REV. 0.11 Apr. 2003 K4C89183AF Revision History Version 0.0 Oct. 2002 - First Release Version 0.01 (Nov. 2002) - Changed die revision from D-die to F-die - Corrected typo - Corrected DQS to DS and QS(DQS -> DS and QS) in AC timing table and timing diagram.

at24C04 code example assembly

Abstract: 24cxx microchip spi e2prom 16k S-29530A S-29530ADPA S-29630A S-29630ADPA S630
Contextual Info: Contents Features. 1 Pin Assignment . 1 Pin Functions . 1 Block Diagram. 2

Contextual Info: Philips Semiconductors 80C51 family programmer’s guide and instruction set 80C51 Family register bank contains eight 1-byte registers 0 through 7. Reset initializes the stack pointer to location 07H, and it is incremented once to start from location OSH, which is the first register R0 of

mcm6830

Abstract: EXORCISER motorola M68MM01A 7642T MC68B54 transistor bf 175 motorola application note 6809 6844 MMS1117 EXORCISER motorola M68MM01A2
Contextual Info: The MS800MM0S Support Elem ents Other NMOS MPUs MC3870 ^ MICROCOMPUTER COMPONENTS CMOS MCUS/ICUS MC14S00B, MC141000/1206 Bipolar 4-Blt slice MPU Fam ilies M2900 TTL , M10800 (MECL) nm os Memories RAM, EPROM, ROM CMOS Memories RAM, ROM MEMORY PRODUCTS Bipoiar Memories

29690A

Abstract: S-29590A DATA010
Contextual Info: 製 造 中 止 品 お 止 廃 よび 特 長･････････････････････････････ 1 ピン配置図･････････････････････････ 1 端子説明･･･････････････････････････ 1

PCF80C39

Abstract: pc880c PCB80C48 PCB80C39 PCB80C49 pc80c C49P
Contextual Info: DEVELOPMENT DATA T h is data sheet contains advance in fo rm a tio n and sp e cificatio n s are subject to change w ith o u t n otice. PCB80C39 JIPCB80C49 SINGLE-CHIP 8-BIT CMOS MICROCONTROLLER DESCRIPTION The PC80CXX fam ily o f single-chip 8-bit CMOS m icrocontrollers consists of:

Contextual Info: DS92LV1260 www.ti.com SNLS134F – DECEMBER 2000 – REVISED APRIL 2013 DS92LV1260 Six Channel 10 Bit BLVDS Deserializer Check for Samples: DS92LV1260 FEATURES DESCRIPTION • The DS92LV1260 integrates six deserializer devices into a single chip. The chip uses a 0.25u CMOS

PRBS-15

Abstract: SCAN921023 SCAN921260
Contextual Info: SCAN921260 X6 1:10 Deserializer with IEEE 1149.1 JTAG and at-speed BIST General Description Features The SCAN921260 integrates six deserializer devices into a single chip. The SCAN921260 can simultaneously deserialize up to six data streams that have been serialized by the

J20R2

Abstract: CM624
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MCM6246 512K x 8 Bit Static Random Access Memory The MCM6246 is a 4,194,304 bit static random access memory organized as 524,288 words of 8 bits, fabricated using high-performance silicon-gate CMOS technology. Static design eliminates the need for external clocks or timing

i251

Abstract: transistor S67 S60 7N transistor s68
Contextual Info: HD66712U Dot-Matrix Liquid Crystal Display Controller/Driver HITACHI Description The HD66712 dot-matrix liquid crystal display controller and driver LSI displays alphanumerics, numbers, and symbols. It can be configured to drive a dot-matrix liquid crystal display under the control of a serial or

K4C89183AF

Contextual Info: K4C89183AF Network-DRAM-II Specification Version 0.01 - 1 - REV. 0.01 Nov. 2002 K4C89183AF Revision History Version 0.0 Oct. 2002 - First Release Version 0.01 (Nov. 2002) - Changed die revision from D-die to F-die - Corrected typo - Corrected DQS to DS and QS(DQS -> DS and QS) in AC timing table and timing diagram.

cjne

Contextual Info: Philips Components-Signetics Application Specific Product Section 1 - Family overview _ PROGRAMMER’S GUIDE AND INSTRUCTION SET Memory Organization Program Memory The 80C51 has separate address spaces for program and data memory. The Program

Contextual Info: K4C89093AF Preliminary 288Mb Network-DRAM-II Specification Version 0.4 - 1 - REV. 0.4 Jul. 2004 K4C89093AF Preliminary Revision History Version 0.0 Nov. 2002 - First Release Version 0.1 (Apr. 2003) - Added 800Mbps(400Mhz) product - Changed operating temperature from Ta to Tc.

Contextual Info: DS92LV1260 www.ti.com SNLS134F – DECEMBER 2000 – REVISED APRIL 2013 DS92LV1260 Six Channel 10 Bit BLVDS Deserializer Check for Samples: DS92LV1260 FEATURES DESCRIPTION • The DS92LV1260 integrates six deserializer devices into a single chip. The chip uses a 0.25u CMOS

VC 5022

Abstract: IC 4002 PIN DIAGRAM S-29530A S-29630A
Contextual Info: Rev.1.11 S-29530A / 29630A CMOS SERIAL E2PROM 2 The S-29530A / 630A series are low power 16K / 32K-bit E PROM with a low operating voltage range. They are organized as 1024-wordx16-bit and 2048-word×16bit, respectively. Each is capable of sequential read,