T74FC Search Results

Contextual Info: 3.3V CMOS ONE-TO-FOUR ADDRESS/CLOCK DRIVER FE A T U R E S : ID T74FC T163344/A/C D E S C R IP T IO N : - 0.5 MICRON CMOS Technology - Typical tSK o (Output Skew) < 250ps - ESD > 2000V per MIL-STD-883, Method 3015; the ability to fanout to memory arrays. Eight banks, each with a fanout of

dt74fct

Contextual Info: HIGH-PERFORMANCE CMOS BUS INTERFACE LATCH D E S C R IP TIO N : FE A T U R E S : - ID T74FC T841A/B/C Equivalent to AMD’s Am29841 bipolar registers in pinout/function, The T74FCT800 series is built using an advanced dual metal CMOS speed and output drive overfull temperature and voltage supply

Contextual Info: ID T74FCT3 573/A 3.3V C M O S OCTAL TRANSPARENT LA TC H E S FE ATURES: DESCRIPTION: • 0.5 MICRON CMOS Technology • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0 • Extended commercial range ot -40°C to +85°C

FCT573T

Contextual Info: ID T74FC T2573T/A T/C T FAST CMOS OCTAL TRANSPARENT LATCH J m ï ï ., D E S C R IP TIO N : FEATURES: - Low input and output leakage <1 |j A max. - Extended commercial range of -40° C to +85° C - CMOS power levels intended for bus oriented applications. The flip-flops appeartransparent to

Contextual Info: 3.3V CMOS 16-BIT BIDIRECTIONAL TRANSCEIVER D E S C R IP TIO N : FE A T U R E S : - 0.5 MICRON CMOS Technology - Typical tSK o (Output Skew) < 250ps - ESD > 2000V per MIL-STD-883, Method 3015; ID T74FC T163245/A/C The FC T 163245/A/C 16-bit transceivers are built using advanced dual

Contextual Info: ID T74FCT3 574/A 3.3V CMOS OCTAL D REGISTERS 3-STATE FE ATURES: DESCRIPTION: • 0.5 MICRON CMOS Technology • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • Extended commercial range ot -40°C to +85°C • V cc = 3.3V ±0.3V, Normal Range or

FCT2373T

Contextual Info: ID T74FC T2373T/A T/C T FAST CMOS OCTAL TRANSPARENT LATCH J m ï ï ., D E S C R IP TIO N : FEATURES: - Low input and output leakage <1 |j A max. - Extended commercial range of -40° C to +85° C - CMOS power levels are intended for bus oriented applications. The flip-flops appeartransparent

TTL 7474

Abstract: 7474 for shift register 7474 shift register 7474 texas instruments ABT8245 SN54ABT8245 SN74ABT8245 tms 3534
Contextual Info: SN54ABT8245, SN74ABT8245 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS SCBS124A - A UGUS T 1992 - REVI SED AUGUS T 1993 ' Members of the Texas Instruments SCOPE Family of Testability Products 1 Compatible With the IEEE Standard 1149.1-1990 JTAG Test Access Port

IDT74HCT

Abstract: S4228 idt71502
Contextual Info: CM O S STATIC RAM 6 4 K 4 K x 16-BIT REGISTERED RAM w /S P C 1 IDT 71502S IDT 71502L FEATURES: DESCRIPTION: • 4K x 16 RAM w ith registered o utp uts, serial or p arallel load and re ad b a ck ca p a b ility In o n ly 48 pin s • Serial P rotocol C hannel a llo w s serial load a n d read b a ck o f RAM

uP1514

Abstract: R3721 IDT79R3721 IDT79R37
Contextual Info: DRAM CONTROLLER FOR THE R3051 FAMILY PRELIMINARY IDT79R3721 Integrated Device Technology, Inc. FEATURES • S upp orts all bus tra nsfers of the R3051 fam ily — P age m ode reads and w rites — Q uad w ord reads — N orm al read o r w rite accesses • 84-pin P LC C

ADO13

Contextual Info: Integrated D evice Technology, Inc. 2 X 4K x 60 DATA/INSTRUCTION CACHE MODULE FOR IDT79R3000 MULTIPROCESSOR _ PRELIMINARY IDT7MB6064 FEATURES: DESCRIPTION: • The ID T 7 M B 606 4 is a 60K-byte high-speed C M O S static RAM cache module constructed on a multilayer epoxy sub­

Contextual Info: ., FAST CMOS OCTAL LATCHED TRANSCEIVER Jm ïï FE A T U R E S : - Low input and output leakage <1 |j A max. - Extended commercial range of -40°C to +85°C - CMOS power levels - True TTL input and output compatibility - - • V oh = 3.3V (typ.) • V ol = 0.3V (typ.)

Contextual Info: B U R R -B R O W N « [ VSP2000 ] CCD SIGNAL PROCESSOR FOR DIGITAL CAMERAS FEATURES DESCRIPTION • CCD SIGNAL PROCESSING Correlated Double Sampling Black Level Clamping 0 to +34dB Gain Ranging High SNR: 53dB T h e V S P 2000 is a co m plete digital cam era IC , p rovid­

s692

Abstract: S693 s684 S687 S694 S69-1 72125
Contextual Info: 14E D INTEGRATED DEVICE IntegratedDeviceTechnotogy Inc • MASS771 0D0373S 2 ■ 256x16,512x16, 1024 x 16 PARALLELTO-SERIAL CMOS FIFO DESCRIPTION: FEATURES: 25ns parallel port a c c e ss time 50MHz serial output port shift rate E a s ily expandable In depth and width

IDT71502

Abstract: PAL16R4C
Contextual Info: CMOS STATIC RAM 64K 4Kx 16-BIT REGISTERED RAM w /SPC’ IDT 71502S IDT 71502L FEATURES: DESCRIPTIO N: • The ID T71502 R egistered RAM is a 65,536 bits h ig h speed static RAM o rga n ized as 4K x 16, w ith a h ig h speed register at the RAM o utputs and serial load and readback c a p a b ility u sing the IDT Se­

IDT72105

Abstract: IDT72115 IDT72125 IDT7212S P28-2
Contextual Info: CMOS PARALLEL-TO-SERIAL FIFO 2 5 6 x 1 6 , 5 1 2 x 1 6 , 1 0 2 4 x 1 6 IDT72105 IDT72115 IDT72125 Integrated Device Technology» Inc* FEATURES: DESCRIPTION: • • • • • The ID T7210 5 /721 15/7 2125s are very high speed, low power dedicated parallel-to-serial FIFO s. These FIFO s

idt71502

Contextual Info: I In te g ra te d D e v ic e T e c h n o lo o y Inc CMOS STATIC RAM 64K 4K X 16-BIT „ REGISTERED RAM w/SPC advance INFC|St7^0°S 5^ 502? FEATURES: DESCRIPTION: • 4K x 16-bit RAM w ith register at outp ut, serial load and readback • D esig n ed fo r m icro p ro g ra m w ritab le co ntro l store

Contextual Info: 3.3V CMOS 16-BIT REGISTER 3-STATE FE A T U R E S : - 0.5 MICRON CMOS Technology - Typical tSK(o) (Output Skew) < 250ps - ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) - 25 mil pitch SSOP, 19.6 mil pitch TSSOP and 15.7 mil pitch TVSOP

Contextual Info: 3.3V CMOS 16-BIT BUFFER/LINE DRIVER FE A T U R E S : - 0.5 MICRON CMOS Technology - Typical tSK o (Output Skew) < 250ps - ESD > 2000V per MlL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) - 25 mil pitch SSOP, 19.6 mil pitch TSSOP and 15.7 mil pitch TVSOP

Contextual Info: 16-BIT CMOS ERROR DETECTION AND CORRECTION UNIT FEATURES IDT39C60 IDT39C60-1 IDT39C60A IDT39C60B • Standard Military Drawing #5962-88613 available for this function • Low-power CEMOS — Military: 100mA max. — Commercial: 85mA (max.) • Fast — Da1a in to Error Delect

Contextual Info: IME D INTEGRATE» DEVICE • MÖSS771 0003^4=1 T 32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT DESCRIPTION: FEATURES: • Fast Detect Correct 16ns max. 24ns (max.) — IDT49C460B 25ns (max.) 30ns (max.) — IDT49C460A 30ns (max.) 36ns (max.) — IDT49C460

uP1514

Contextual Info: DRAM CONTROLLER FOR THE R3051 FAMILY PRELIMINARY IDT79R3721 Integrated Device Technology, Inc. FEATURES • S upp orts all bus tra nsfers of the R3051 fam ily — P age m ode reads and w rite s — Q ua d w ord reads — N orm al read or w rite accesses • 84-pin PLC C

E5771

Abstract: IDT72105 IDT72115 IDT72125 P28-2
Contextual Info: INTEGRATED DEVICE 47E D Bi MÖ2S771 DOO'iMTl fl BlI DT IDT72105 IDT72115 IDT72125 CMOS PARALLEL-TO-SERIAL FIFO 256x16, 512x16,1024x16 T - * f é - 3 ; r Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • • • • • T h e ID T7210 5 /7 2 1 1 5 /7 2 1 25 s are very high speed, low

uP1514

Abstract: IDT79R3721 DRAM 4M x 8 25mhz SIGNAL PATH DESIGNER cs 9051 A25A
Contextual Info: DRAM CONTROLLER FOR THE R3051 FAMILY PRELIMINARY IDT79R3721 Integrated D evice T ech n olo gy, Inc. FEATURES S upp orts all bu s tra nsfers of the R3051 fam ily — P age m ode reads and w rites — Q uad w ord reads — N orm al read o r w rite accesses 84-pin PLC C