MASS771 Search Results

s692

Abstract: S693 s684 S687 S694 S69-1 72125
Contextual Info: 14E D INTEGRATED DEVICE IntegratedDeviceTechnotogy Inc • MASS771 0D0373S 2 ■ 256x16,512x16, 1024 x 16 PARALLELTO-SERIAL CMOS FIFO DESCRIPTION: FEATURES: 25ns parallel port a c c e ss time 50MHz serial output port shift rate E a s ily expandable In depth and width

eerl

Abstract: ym oca QQ11
Contextual Info: INTEGRATE» DEVICE SflE D • 4025771 R3081 BLOCK DIAGRAM BrCond 3:2,0 C lock G enerator Unit/ C lock Doubler M aster Pipeline Control System Control C oprocessor Integer CPU Core Floating Point C oprocessor (CP1) (CP0) Exception/Control Registers G eneral Registers

Contextual Info: LOW POWER 3.3V CMOS FAST SRAM 256K 32K x 8-BIT PRELIMINARY IDT71V256SA In te g ra te d D evice T echnology, Inc. FEATURES DESCRIPTION • Ideal for high-perform ance processor secondary cache • Fast access times: — 20/25ns • Low standby current (maximums):

j32-1

Abstract: idt71256
Contextual Info: integrated 5flE D device 4A25771 CMOS STATIC RAM 256K 32K x 8-BIT D011b7E MM? « I D T IDT71256S IDT71256L Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • High-speed address/chip select time — Military: 25/30/35/45/55/70/85/100/120/150ns (max.)

Contextual Info: 3.3V CMOS 36-BIT REGISTERED TRANSCEIVER WITH 5 VOLT TOLERANT I/O IDT74LVCH36501A IDT74LVCH362501A ADVANCE INFORMATION FEATURES: DESCRIPTION: • Common features: These 36-bit registered transceivers are built using ad­ vanced dual metal CMOS technology. These high-speed, low

PicoGate

Contextual Info: i V I D 3.3V CMOS SINGLE BUS BUFFER GATE W ITH 3-STATE O UTPUT AND 5 VOLT TOLERANT I/O T FEA TU RES: - IDT74LVC1G126A D E S C R IP T IO N : 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0 0.65mm pitch PSOP package

Contextual Info: IN T E GR AT ED 3AE D DEVIC E • 4 Ô 2 S 77 1 0 Q 0 7 b S b M ■ IDT _ T-M9-17- 2>2~ RISCore RISC CPU PROCESSOR PRELIMINARY IDT79R3500A Integrated Device Technology, Inc. FEATURES: Supports independent multiword block refill of both the

Contextual Info: MULTILEVEL PIPELINE REGISTERS IDT29FCT520AT/BT/CT/DT IDT29FCT521AT/BT/CT/DT Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • • • • The 1DT29FCT520AT/BT/CT/DT and IDT29FCT521AT/ BT/CT/DT each contain four 8-bit positive edge-triggered registers. These may be operated as a dual 2-level or as a

Contextual Info: FAST CMOS OCTAL REGISTER TRANSCEIVER WITH PARITY Integrated Device Technology, Inc* FEATURES PRELIMINARY IDT73210/A/B IDT73211/A/B 73210/211 Single-level pipeline register from Port A to Port B 73210 Two level pipeline register from Port B to Port A 73211 Single level pipeline register from Port B to Port A

Contextual Info: »^rry?,r t. ZLgî7Ηz INTEGRATED DEVICE 3 ÔE D • M Û 2 S 771 QDDbflbB M ■ IDT '* - 4 t - 2 3 - m IDT7M137 32K X 8 CMOS DUAL-PORT STATIC RAM MODULE Integrated D evice T ech n o logy, Inc. FEATURES: the higher order addresses A L 12-14 and A R 12-14 to select