SI5330 Search Results

CONN TRBLK 4

Abstract: C0402X7R100-104K HEADER_1X3
Contextual Info: Si 5 3 3 0 1 / 4 - E VB Si53301/4 E VALUATION B OARD U SER ’ S G U ID E Description EVB Features The Si53301/4-EVB is used for evaluation of the Si533xx family of low-jitter clock buffers/level translators. As shipped from the factory, this evaluation board has the Si53301 device installed. The entire

Si53308

Abstract: Si533x
Contextual Info: Si53308 D U A L 1 : 3 L O W - J I T T E R B UFFER / L EVEL T RANSLATOR Features Ordering Information: See page 28. Storage Telecom  Industrial  Servers  Backplane clock distribution Q2 Q3 Q3 Q4 Q4 26 25 27 28 29 30 Vref Generator DIVA SFOUTA[1] SFOUTA[0]

Contextual Info: Si53302 1 : 1 0 L OW J I T T E R U NIVERSAL B U FF E R /L EVEL T RANSLATOR WITH 2 : 1 I NPUT M UX Features Ordering Information: See page 29. Applications 34 37 35 36 38 39 40 41 The Si53302 is an ultra low jitter ten output differential buffer with pin-selectable

Si53304

Contextual Info: Si53304 1:6 L OW J I T T E R U NIVERSAL B U F F E R /L EVEL T RANSLATOR WITH 2 : 1 I NPUT M UX A N D I NDIVIDUAL OE Features         6 differential or 12 LVCMOS outputs  Ultra-low additive jitter: 100 fs rms  Wide frequency range: 1 to 725 MHz

Si5330A-B00200-GM

Contextual Info: Si5330 1 . 8 / 2 . 5 / 3 . 3 V L O W - J I T T E R, L O W - S K EW C L O C K B U F F E R / L E V E L TR A N S L A T O R Features 18 OEB 19 CLK1A 17 20 CLK1B 16 21 VDDO1 15 22 VDDO2 CLK2A CLK2B GND GND RSVD_GND 6 7 VDD RSVD_GND 5 Functional Block Diagram 23

si5330

Contextual Info: Si5330 1.8/2.5/3.3 V L O W J I TT E R, L OW S KE W C LO CK B UF F ER /L E V EL T RA NS L AT OR Features  Factory-programmed mux selects  Wide frequency range between 1 of 2 inputs and provides LVPECL, LVDS: 5 to 710 MHz multiple precision, low-skew

Contextual Info: Si53304 1:6 L OW J I T T E R U NIVERSAL B U F F E R /L EVEL T RANSLATOR WITH 2 : 1 I NPUT M UX A N D I NDIVIDUAL OE Features         6 differential or 12 LVCMOS outputs  Ultra-low additive jitter: 45 fs rms Wide frequency range: 1 to 725 MHz 

cross reference guide

Abstract: Silabs SI53302-B-GM
Contextual Info: Si53302 1 : 1 0 L OW J I T T E R U NIVERSAL B U FF E R /L EVEL T RANSLATOR WITH 2 : 1 I NPUT M UX Features         10 differential or 20 LVCMOS outputs Ultra-low additive jitter: 45 fs rms Wide frequency range: 1 to 725 MHz  Any-format input with pin selectable

qfn 48 7x7 stencil

Abstract: SI53302-B-GM 53302-B-GM
Contextual Info: Si53302 1 : 1 0 L OW J I T T E R U NIVERSAL B U FF E R /L EVEL T RANSLATOR WITH 2 : 1 I NPUT M UX Features Ordering Information: See page 25. Applications Q6 Q6 VDDOB 34 37 35 38 39 DIVA 1 33 DIVB SFOUTA[1] SFOUTA[0] 2 32 3 31 SFOUTB[1] SFOUTB[0] Q2 4 Q2 5

Contextual Info: Si53306 1 : 4 L O W - J ITTER U N I V E R S A L B U F F E R / L E V E L T R A N S L A T O R Features Independent VDD and VDDO : 1.8/2.5/3.3 V 1.2/1.5 V LVCMOS output support Selectable LVCMOS drive strength to tailor jitter and EMI performance Small size: 16-QFN 3 mm x 3 mm

536FS

Contextual Info: Si53301 1:6 L OW J I T T E R U NIVERSAL B U F F E R /L EVEL T RANSLATOR WITH 2 : 1 I NPUT M UX Features Ordering Information: See page 28. Storage Telecom  Industrial  Servers  Backplane clock distribution Q3 Q4 Q4 29 28 27 26 25 Functional Block Diagram

Si53303

Contextual Info: Si53303 D UAL 1:5 L OW J I T T E R B UFFER / L EVEL T RANSLATOR Features         10 differential or 20 LVCMOS outputs Ultra-low additive jitter: 100 fs rms Wide frequency range: 1 to 725 MHz Any-format input with pin selectable

si5330

Contextual Info: Si53301 1:6 L OW J I T T E R U NIVERSAL B U F F E R /L EVEL T RANSLATOR WITH 2 : 1 I NPUT M UX Features Ordering Information: See page 24. Applications Q0 Q3 Q3 Q4 Q4 25 1 24 DIVB 2 23 SFOUTB[1] 3 22 SFOUTB[0] 4 GND PAD 5 21 Q5 20 Q5 VDDOB 16 VREF CLK_SEL

Si53305

Abstract: MO-220 7x7 0.4 pitch SI53305-B-GM
Contextual Info: Si53305 1 : 1 0 L OW J I T T E R U NIVERSAL B U FF E R /L EVEL T RANSLATOR WITH 2 : 1 I NPUT M UX A N D I NDIVIDUAL OE Features Ordering Information: See page 25. Applications CLK_SEL Q5 Q5 Q6 Q6 VDDOB 34 37 36 35 38 OE7 SFOUT[1] OE2 SFOUT[0] 1 33 2 32 OE1

FA-238 25.0000MB-C3

Abstract: C0402X7R100
Contextual Info: Si 5 3 3 8 - EVB Si5330/34/35/38 E VALUATION B OA RD U SER ’ S G UIDE Description EVB Features The Si5338-EVB is used for evaluating the Si5330/34/ 35/38 family of any-frequency, any-output clock generators and clock buffers.  Fully powered from a single USB port.

Contextual Info: Si53301 1:6 L OW J I T T E R U NIVERSAL B U F F E R /L EVEL T RANSLATOR WITH 2 : 1 I NPUT M UX Features Storage Telecom  Industrial  Servers  Backplane clock distribution Q3 Q4 Q4 30 29 28 27 26 25 1 24 DIVB SFOUTA[1] 2 23 SFOUTB[1] SFOUTA[0] 3 Q0

Si53306

Abstract: Si53306-B-GM 5310A
Contextual Info: Si53306 1 : 4 L O W - J ITTE R U N I V E R S A L B U F F E R / L E V E L T R A N S L A T O R Features  4 differential or 8 LVCMOS outputs  Ultra-low additive jitter: 45 fs rms  Wide frequency range: 1 to 725 MHz   Any-format input with pin selectable

AN408

Abstract: SI5330A-a00200-gm SI5330F si5330 JESD78 Si5334 Si5338 SSTL-18 SI5330B-A00206-GM SI5330J-A00223-GM
Contextual Info: Si5330 1 . 8 / 2 . 5 / 3 . 3 V L O W J I T T E R, L O W S K E W C L O C K B U F F E R / L E V E L TR A N S L A T O R Features Functional Block Diagram OEB 18 CLK1B IN3 16 IN2 17 VDDO0 19 15 RSVD_GND 14 GND GND RSVD_GND RSVD_GND 13 PCI Express 2.0/3.0  Fibre Channel

Si5338-EVB

Abstract: Si533x Si5334 si5330 Si533x-EVB s7 tp3 si5330 data sheet AN408 Si5338 C8051F340
Contextual Info: Si 5 3 3 8 - EVB Si5330/34/38 E VALUATION B OARD U SER ’ S G UIDE Description EVB Features The Si5338-EVB is used for evaluating the Si5330/34/ 38 family of any-frequency, any-output clock generators and clock buffers.  Fully powered from a single USB port.

si514

Abstract: SI510
Contextual Info: AN765 T HERMAL A NALYSIS OF S I L I C O N L ABS T I M I N G D EVICES 1. Introduction The junction temperature of semiconductor devices affects reliability and performance of Integrated Circuits ICs , including timing devices. This application note provides the following:

what is slew rate

Contextual Info: AN766 U NDERSTANDING A N D O PTIMIZING C L O C K B UFFER ’ S A D D IT I V E J ITTER P E R F OR MA N C E 1. Introduction This application note details the various contributions to a clock distribution’s buffer’s additive phase noise performance and how to optimize performance without increasing costs.

Si5338

Abstract: Si533x SI5338A Si5338C SI5334C
Contextual Info: Industry’s First Any-Rate, Any-Output Clock Generators One Stop for Customers’ Timing Needs Any-Rate Precision Clocks Single/Dual/Quad/Any-Rate Any-Rate Frequency XO/VCXOs Crystal-Less Oscillators Any-Rate Clock Generators/Buffers Broad portfolio based on proprietary DSPLLTM and MultiSynth technology:

si5332

Abstract: SMA103A qfn 3X3 land pattern 5310A
Contextual Info: Si53322 1:2 L OW - J I T T E R LVPECL C L O C K B UFFER Features  2 LVPECL outputs   Ultra-low additive jitter: 45 fs rms   Wide frequency range: dc to 1250 MHz   Universal input stage accepts  differential or LVCMOS clock VDD: 2.5 / 3.3 V

Contextual Info: SPEAr1340 Dual-core Cortex A9 HMI embedded MPU Datasheet − preliminary data Features • CPU subsystem: – 2x ARM Cortex A9 cores, up to 600 MHz – 32+32 KB L1 caches per core, with parity check – Shared 512 KB L2 cache – Accelerator coherence port ACP