SI53301 Search Results

CONN TRBLK 4

Abstract: C0402X7R100-104K HEADER_1X3
Contextual Info: Si 5 3 3 0 1 / 4 - E VB Si53301/4 E VALUATION B OARD U SER ’ S G U ID E Description EVB Features The Si53301/4-EVB is used for evaluation of the Si533xx family of low-jitter clock buffers/level translators. As shipped from the factory, this evaluation board has the Si53301 device installed. The entire

536FS

Contextual Info: Si53301 1:6 L OW J I T T E R U NIVERSAL B U F F E R /L EVEL T RANSLATOR WITH 2 : 1 I NPUT M UX Features Ordering Information: See page 28. Storage Telecom  Industrial  Servers  Backplane clock distribution Q3 Q4 Q4 29 28 27 26 25 Functional Block Diagram

si5330

Contextual Info: Si53301 1:6 L OW J I T T E R U NIVERSAL B U F F E R /L EVEL T RANSLATOR WITH 2 : 1 I NPUT M UX Features Ordering Information: See page 24. Applications Q0 Q3 Q3 Q4 Q4 25 1 24 DIVB 2 23 SFOUTB[1] 3 22 SFOUTB[0] 4 GND PAD 5 21 Q5 20 Q5 VDDOB 16 VREF CLK_SEL

Contextual Info: Si53301 1:6 L OW J I T T E R U NIVERSAL B U F F E R /L EVEL T RANSLATOR WITH 2 : 1 I NPUT M UX Features Storage Telecom  Industrial  Servers  Backplane clock distribution Q3 Q4 Q4 30 29 28 27 26 25 1 24 DIVB SFOUTA[1] 2 23 SFOUTB[1] SFOUTA[0] 3 Q0

si514

Abstract: SI510
Contextual Info: AN765 T HERMAL A NALYSIS OF S I L I C O N L ABS T I M I N G D EVICES 1. Introduction The junction temperature of semiconductor devices affects reliability and performance of Integrated Circuits ICs , including timing devices. This application note provides the following:

what is slew rate

Contextual Info: AN766 U NDERSTANDING A N D O PTIMIZING C L O C K B UFFER ’ S A D D IT I V E J ITTER P E R F OR MA N C E 1. Introduction This application note details the various contributions to a clock distribution’s buffer’s additive phase noise performance and how to optimize performance without increasing costs.

si5332

Abstract: SMA103A qfn 3X3 land pattern 5310A
Contextual Info: Si53322 1:2 L OW - J I T T E R LVPECL C L O C K B UFFER Features  2 LVPECL outputs   Ultra-low additive jitter: 45 fs rms   Wide frequency range: dc to 1250 MHz   Universal input stage accepts  differential or LVCMOS clock VDD: 2.5 / 3.3 V

Si53308

Abstract: Si533x
Contextual Info: Si53308 D U A L 1 : 3 L O W - J I T T E R B UFFER / L EVEL T RANSLATOR Features Ordering Information: See page 28. Storage Telecom  Industrial  Servers  Backplane clock distribution Q2 Q3 Q3 Q4 Q4 26 25 27 28 29 30 Vref Generator DIVA SFOUTA[1] SFOUTA[0]

Contextual Info: Si53302 1 : 1 0 L OW J I T T E R U NIVERSAL B U FF E R /L EVEL T RANSLATOR WITH 2 : 1 I NPUT M UX Features Ordering Information: See page 29. Applications 34 37 35 36 38 39 40 41 The Si53302 is an ultra low jitter ten output differential buffer with pin-selectable

Si53307-B-GM

Contextual Info: S i533 0 7 2:2 L O W J I T T E R U N I V E R S A L B U F F E R/L E V E L T R A N S L A T O R Features  2 differential or 4 LVCMOS outputs   Ultra-low additive jitter: 45 fs rms  Wide frequency range: 1 to 725 MHz   Any-format input with pin selectable

Contextual Info: Si53304 1:6 L OW J I T T E R U NIVERSAL B U F F E R /L EVEL T RANSLATOR WITH 2 : 1 I NPUT M UX A N D I NDIVIDUAL OE Features         6 differential or 12 LVCMOS outputs  Ultra-low additive jitter: 45 fs rms Wide frequency range: 1 to 725 MHz 

cross reference guide

Abstract: Silabs SI53302-B-GM
Contextual Info: Si53302 1 : 1 0 L OW J I T T E R U NIVERSAL B U FF E R /L EVEL T RANSLATOR WITH 2 : 1 I NPUT M UX Features         10 differential or 20 LVCMOS outputs Ultra-low additive jitter: 45 fs rms Wide frequency range: 1 to 725 MHz  Any-format input with pin selectable

Contextual Info: Si53306 1 : 4 L O W - J ITTER U N I V E R S A L B U F F E R / L E V E L T R A N S L A T O R Features Independent VDD and VDDO : 1.8/2.5/3.3 V 1.2/1.5 V LVCMOS output support Selectable LVCMOS drive strength to tailor jitter and EMI performance Small size: 16-QFN 3 mm x 3 mm

Contextual Info: AN775 Si5328: S Y N C H R ON OU S E THERNET * C OMPLIANCE TEST R EPORT 1. Introduction Synchronous Ethernet SyncE is a key solution used to distribute Stratum 1 traceable frequency synchronization over packet networks, which will ultimately drive the interoperability of carrier Ethernet and legacy networks. Silicon

Si53340-B-GM

Abstract: si53340 SMA103A 5310A
Contextual Info: Si53340 1:4 L O W - J I T T E R LV DS C LO C K B U F F E R WITH 2:1 INPUT MUX Features      4 LVDS outputs  Ultra-low additive jitter: 45 fs rms  Wide frequency range: dc to 1250 MHz  2:1 input mux  Universal input stage accepts

5310A

Contextual Info: Si53323 1:4 L O W - J I T T E R LV PECL C L O C K B U F F E R WI TH 2 : 1 I N P U T M UX Features      4 LVPECL outputs  Ultra-low additive jitter: 45 fs rms  Wide frequency range: dc to 1250 MHz  2:1 input mux  Universal input stage accepts

Si53306

Abstract: Si53306-B-GM 5310A
Contextual Info: Si53306 1 : 4 L O W - J ITTE R U N I V E R S A L B U F F E R / L E V E L T R A N S L A T O R Features  4 differential or 8 LVCMOS outputs  Ultra-low additive jitter: 45 fs rms  Wide frequency range: 1 to 725 MHz   Any-format input with pin selectable

Contextual Info: AN739 E STIMATING C LOCK T REE J I T T E R 1. Introduction High speed, high performance timing applications often require a combination of XO/VCXOs, clock generators, clock buffers and jitter cleaning clocks to satisfy system timing requirements. Each component in the clock tree

SI510

Contextual Info: Timing Selector Guide SPRING 2014 HIGH PERFORMANCE CUSTOMIZABLE FREQUENCY FLEXIBILITY 2-WEEK LEAD TIME 2 / C L O C K A N D O S C I L L AT O R S E L E C T O R Timing Solutions Comprehensive — complete portfolio of oscillators, clock generators, clock buffers and jitter attenuators