SI5338 Search Results

AN411

Abstract: Si5338 4042AS AVAR PICAL 2 refcl
Contextual Info: A N 4 11 C ONFIGURING T H E Si5338 1. Introduction The Si5338 is a highly flexible and configurable clock generator/clock buffer. A block diagram of the Si5338 is shown in Figure 1. 7, 24 Optional XTAL IN1 IN2 VDD Si5338 20 Osc MultiSynth ÷M0 1 22 ÷R0 16

Si5338C

Abstract: Si5338 AN562 JESD78 SSTL-18 UM10204 3G-SDI serializer Si5338A SDI SERIALIZER Si5338s
Contextual Info: Si5338 I 2 C - P R O GRA MM A B LE A NY - F R E Q U E N C Y, A NY - O UTPUT Q UAD C LOCK G ENERATOR Features Applications CLK0B VDDO0 SDA 22 21 20 19 18 CLK1A IN2 2 17 CLK1B IN3 3 16 VDDO1 GND GND Pad IN4 4 15 VDDO2 IN5 5      Any-frequency clock conversion

Si5338

Abstract: Si533x si5338b stk 282 STK 290 010 stk 2250 stk 282 270 BY165 si5330 data sheet AN408
Contextual Info: Si5338 I 2 C - P R O G R A M M A B LE A N Y - F R E Q U E N C Y, A N Y -O UTPU T Q U A D C L OC K G E N E R A T O R Features Applications CLK0B VDDO0 SDA 22 21 20 19 18 CLK1A IN2 2 17 CLK1B IN3 3 16 VDDO1 GND GND Pad IN4 4 15 VDDO2 IN5 5     Any-frequency clock conversion

si5338

Abstract: AN473 Si5338-EVB B10MHz
Contextual Info: AN473 C ONFIGURING T H E Si5338 E VALUATION B OARD I N Z ERO D ELAY M ODE 1. Introduction The Si5338 can be configured in zero delay mode to help minimize the input-to-output delay. This application note provides details on setting up an Si5338 evaluation board Si5338-EVB in zero delay mode. In this example, the

Contextual Info: Si5338 I 2 C - P R O GRA MM A B LE A NY - F R E Q U E N C Y, A NY - O UTPUT Q UAD C LOCK G ENERATOR Features Applications CLK0B VDDO0 SDA 22 21 20 19 18 CLK1A IN2 2 17 CLK1B IN3 3 16 VDDO1 GND GND Pad IN4 4 15 VDDO2 IN5 5      Any-frequency clock conversion

Phase Frequency detector

Abstract: Si5338
Contextual Info: Si5338 I 2 C - P R O GRA MM A B LE A NY - F R E Q U E N C Y, A NY - O UTPUT Q UAD C LOCK G ENERATOR Features Applications CLK0B VDDO0 SDA 22 21 20 19 18 CLK1A IN2 2 17 CLK1B IN3 3 16 VDDO1 GND GND Pad IN4 4 15 VDDO2 IN5 5      Any-frequency clock conversion

Si5338

Contextual Info: Si5338 I 2 C - P ROGR AMMABLE A NY - R ATE , A N Y -O UTPUT Q UAD C LOCK G E N E R A T O R Features Gigabit Ethernet PCI Express 2.0 OC-3/12, SFI-5 Processor, memory clocking     Broadcast video xDSL PON T1/E1 SDA VDDO0 CLK0B CLK1A IN2 CLK1B VDDO1

Si5338

Abstract: Si5338s Si5338-EVB si5330 SI5338C-AXXXXXGM Si5338X-A-GM
Contextual Info: Si5338 I 2 C - P R O GRA MM A B LE A NY - F R E Q U E N C Y, A NY - O UTPUT Q UAD C LOCK G ENERATOR Features Applications CLK0B VDDO0 SDA 22 21 20 19 18 CLK1A IN2 2 17 CLK1B IN3 3 16 VDDO1 GND GND Pad IN4 4 15 VDDO2 IN5 5      Any-frequency clock conversion

FA-238 25.0000MB-C3

Abstract: C0402X7R100
Contextual Info: Si 5 3 3 8 - EVB Si5330/34/35/38 E VALUATION B OA RD U SER ’ S G UIDE Description EVB Features The Si5338-EVB is used for evaluating the Si5330/34/ 35/38 family of any-frequency, any-output clock generators and clock buffers.  Fully powered from a single USB port.

Contextual Info: Si5338 I 2 C -P ROG RA MMA BL E A N Y - R A T E , A NY -O UT P UT Q UA D C L O C K G E NE R AT O R Features Zero ppm frequency error  Flexible input clock buffer crystal: 8 to 30 MHz clock: 5 to 350 MHz Differential clock: 5 to 700 MHz  External

385-FRLS-NV-M

Contextual Info: Si5338/56-PROG-EVB S i 5 3 3 8 / S i 5 3 5 6 F I E L D P R O G R A M M I N G K I T U S E R ’S G U I D E Description Field Programming Kit Features The Si5338/Si5356 Field Programming Kit provides all of the tools necessary for writing a new configuration file

Si5338-EVB

Abstract: Si533x Si5334 si5330 Si533x-EVB s7 tp3 si5330 data sheet AN408 Si5338 C8051F340
Contextual Info: Si 5 3 3 8 - EVB Si5330/34/38 E VALUATION B OARD U SER ’ S G UIDE Description EVB Features The Si5338-EVB is used for evaluating the Si5330/34/ 38 family of any-frequency, any-output clock generators and clock buffers.  Fully powered from a single USB port.

Si5338

Abstract: SI5338C-A-GM schematic diagram of a router
Contextual Info: Si5338 I 2 C - P R O GRA MM A B LE A NY - F R E Q U E N C Y, A NY - O UTPUT Q UAD C LOCK G ENERATOR Features Applications CLK0B VDDO0 SDA 22 21 20 19 18 CLK1A IN2 2 17 CLK1B IN3 3 16 VDDO1 GND GND Pad IN4 4 15 VDDO2 IN5 5      Any-frequency clock conversion

SI5338A

Abstract: Si5338 si5338b si5338c Si5338CA00100-GM SI5338D SI5338J SI5338L
Contextual Info: Si5338 I 2 C - P ROGR AMMABLE A NY - R ATE , A N Y -O UTPUT Q UAD C LOCK G E N E R A T O R Features Applications CLK0B VDDO0 SDA 22 21 20 19 18 CLK1A IN2 2 17 CLK1B IN3 3 16 VDDO1 GND GND Pad IN4 4 15 VDDO2 IN5 5     Any-rate clock conversion MSAN/DSLAM/PON

Contextual Info: AN619 Manually Generating an Si5351 Register Map 1. Introduction The Si5351 is a highly flexible and configurable clock generator and VCXO. A block diagram of the Si5351 programmable clock IC is shown in Figure 1. To support this flexibility, Silicon Labs has created ClockBuilder

Si5338

Abstract: Si533x SI5338A Si5338C SI5334C
Contextual Info: Industry’s First Any-Rate, Any-Output Clock Generators One Stop for Customers’ Timing Needs Any-Rate Precision Clocks Single/Dual/Quad/Any-Rate Any-Rate Frequency XO/VCXOs Crystal-Less Oscillators Any-Rate Clock Generators/Buffers Broad portfolio based on proprietary DSPLLTM and MultiSynth technology:

Contextual Info: DSP Development Kit, Stratix V Edition User Guide DSP Development Kit, Stratix V Edition User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com UG-01119-1.1 Feedback Subscribe 2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos

Contextual Info: 100G Development Kit, Stratix V GX Edition User Guide 100G Development Kit, Stratix V GX Edition User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com UG-01111-1.1 Feedback Subscribe 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos

Contextual Info: Arria V GX FPGA Development Kit User Guide Arria V GX FPGA Development Kit User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com UG-01112-1.0 Feedback Subscribe 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos

capacitor rse 104

Abstract: Si5356B-A00322-GM SI5356B
Contextual Info: Si5356B * I 2C P ROGRAMMABLE , A NY - F R E Q U E N C Y 1 – 2 0 0 M H Z , Q UAD F R E Q U E N C Y 8-O UTPUT C LOCK G ENERATOR Features          Generates any frequency from 1 to  200 MHz on each of the 4 output banks Eight CMOS clock outputs

schematic diagram atx Power supply 500w

Abstract: pioneer PAL 012A 1000w inverter PURE SINE WAVE schematic diagram 600va numeric ups circuit diagrams winbond bios 25064 TLE 9180 infineon smsc MEC 1300 nu TBE schematic diagram inverter 2000w DK55 circuit diagram of luminous 600va UPS
Contextual Info: QUICK INDEX NEW IN THIS ISSUE! Detailed Index - See Pages 3-24 Digital Signal Processors, iCoupler , iMEMS® and iSensor . . . . . 805, 2707, 2768-2769 Connectors, Cable Assemblies, IC Sockets . . . . . . . . . . . 28-568 RF Connectors . . . . . . . . . . . . . . . . . . . . . . Pages 454-455

Si5330A-B00200-GM

Contextual Info: Si5330 1 . 8 / 2 . 5 / 3 . 3 V L O W - J I T T E R, L O W - S K EW C L O C K B U F F E R / L E V E L TR A N S L A T O R Features 18 OEB 19 CLK1A 17 20 CLK1B 16 21 VDDO1 15 22 VDDO2 CLK2A CLK2B GND GND RSVD_GND 6 7 VDD RSVD_GND 5 Functional Block Diagram 23

si5335

Abstract: si5335d Si5335B
Contextual Info: Si5335 W EB -C USTOMIZABLE , A NY - F REQUENCY, A NY - O U TP U T Q UAD C LOCK G ENERATOR /B U FF E R Features CLK0B VDDO0 P2 21 20 19 18 CLK1A XB/CLKINB 2 17 CLK1B      Processor and FPGA clocking MSAN/DSLAM/PON Fibre Channel, SAN Telecom line cards

Contextual Info: Si5356A I 2C P ROGRAMMABLE , A NY - F R E Q U E N C Y 1 – 2 0 0 M H Z , Q UAD F R E Q U E N C Y 8-O UTPUT C LOCK G ENERATOR Features          Generates any frequency from 1 to  200 MHz on each of the 4 output banks Programmable frequency configuration 