SY100E Search Results

Contextual Info: 3V LVTTL-TO-DIFFERENTIAL LVPECL AND DIFFERENTIAL LVPECL-TO-LVTTL TRANSLATOR SY10EPT28L SY100EPT28L FINAL FEATURES • 3.3V ±10% power supply ■ Guaranteed AC parameters over temperature: fMAX > 275MHz LVTTL ■ < 2ns LVPECL-to-LVTTL propagation delay ■ < 600ps LVTTL-to-LVPECL propagation delay

Contextual Info: PECL-TO-CML TRANSLATOR w/o ENABLE FEATURES • ■ ■ ■ ■ ■ ■ ■ SY100ELT982 DESCRIPTION Up to 1.25Gbps operation 25mA peak drive current Adjustable output current Separate output enable Differential inputs for data 75KΩ input pull-down resistor

elt25

Contextual Info: DIFFERENTIAL ECL-to-TTL TRANSLATOR FEATURES • ■ ■ ■ ■ DESCRIPTION 2.6ns typical propagation delay Differential ECL inputs 24mA TTL outputs Flow-through pinouts Available in 8-pin SOIC package The SY100ELT25 is a differential ECL-to-TTL translator. Because ECL levels are used, a +5V, –5.2V

Contextual Info: QUINT LVPECL-TO-PECL OR PECL-TO-LVPECL TRANSLATOR DESCRIPTION FEATURES • ■ ■ ■ ■ ■ SY100E417 3.3V and 5V power supplies required Also, supports LVPECL-to-PECL translation 500ps propagation delays Fully differential design Differential line receiver capability

Contextual Info: Precision Edge SY10ELT20V SY100ELT20V FINAL FEATURES • ■ ■ ■ ■ ■ ■ 3.3V and 5V power supply options 300ps typical propagation delay Low power Differential PECL output PNP TTL input for minimal loading Flow-through pinouts Available in 8-pin SOIC package

Contextual Info: 5V/3.3V 2.5Gbps VARIABLE OUTPUT SWING DIFFERENTIAL RECEIVER SY100EP16VS FINAL FEATURES • 3.3V and 5V power supply options ■ Fast output transitions <160ps tr / tf ECL Pro ■ Guaranteed operation over –40°C to +85°C temperature range ■ Functionally equivalent to SY88927V and

Contextual Info: 3.3V 1:4 CLOCK DISTRIBUTION FEATURES • ■ ■ ■ ■ ■ ■ DESCRIPTION The SY100EL15L is a low skew 1:4 clock distribution IC designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power

PS235

Contextual Info: *SYNERGY SY10EL52 SY100EL52 DIFFERENTIAL DATA AND CLOCK D FLIP-FLOP S E M IC O N D U C T O R FEATURES • DESCRIPTION ■ 3 65ps propagation delay The c lo c k ■ 2.0GHz toggle frequency S Y 1 0 /1 0 0 E L 5 2 D flip - f lo p s a re w it h d if fe r e n t ia l d a ta , d if fe r e n t ia l

Contextual Info: * 5 V / 3 . 3 V ^2. + 4 /6 C L O C K SYNERGY Clockworks G E N E R A T I O N C H IP SY100EL38/L SEMICONDUCTOR DESCRIPTION FEATURES 3.3V and 5V power supply options 50ps output-to-output skew Synchronous enable/disable M aster Reset for synchronization Internal 75KQ input pull-down resistors

Contextual Info: c* SY10EL01 SY100EL01 4-INPUT OR/NOR SYNERGY SEMICONDUCTOR FEATURES DESCRIPTION • 230ps propagation delay The SY10/100EL01 are 4-input OR/NOR gates. These devices are functionally equivalent to the E101 devices, with higher performance capabilities. With propagation

Contextual Info: *SYNERGY SY10EL04 SY100EL04 2-INPUT AND/NAND S E M IC O N D U C T O R FEATURES DESCRIPTION • 240ps propagation delay The S Y 1 0/1 0 0 E L 0 4 are 2 -in p u t A N D /N A N D gates. T hese devices are function a lly eq u iva le nt to the E104 d e vice s, w ith h ig h e r p e rfo rm a n ce c a p a b ilitie s .

Contextual Info: * C lo c k w o rk s SY10EL34/L SY100EL34/L 5V/3.3V +2, +4, ^8 CLOCK GENERATION CHIP SYNERGY SEMICONDUCTOR FEATURES DESCRIPTION 3.3V and 5V power supply options 50ps ou tput-to-output skew Synchronous enable/disable Master Reset fo r synchronization Internal 75KQ input pull-down resistors

Contextual Info: * SY10EL35 SY100EL35 JK FLIP-FLOP SYNERGY S E M IC O N D U C T O R DESCRIPTION FEATURES • 525ps propagation delay The S Y 10 /1 00EL35 are high-speed JK Flip-Flops. The J/K data enters the m aster portion of the flip -flop when the clock is LO W and is tran sfe rre d to the slave and,

100E196

Contextual Info: * C lo c k w o rk s SY10E196 SY100E196 P R O G R A M M A B L E DELAY CHIP WITH A N A L O G INPUT SYNERGY S E M IC O N D U C T O R DESCRIPTION FEATURES • Up to 2ns delay range ■ Extended 100E V ee range of -4.2V to -5.5V ■ ~20ps digital step resolution

transistor k81

Abstract: SY100EP33VKG SY100EP33VZC SY100EP33VZCTR SY10EP33VKC SY10EP33VKCTR SY10EP33VZC SY10EP33VZCTR EP-33
Contextual Info: SY10EP33V/SY100EP33V 5V/3.3V, 4GHz, ÷4 PECL/LVPECL Divider Precision Edge General Description The SY10/100EP33V is an integrated ÷4 divider. The VBB pin, an internally-generated voltage supply, is ECL Pro available to this device only. For single-ended input

E160

Abstract: E193 MC10193 SY100E193 SY10E193
Contextual Info: Micrel, Inc. SY10E193 SY100E193 SY10E193 ERROR DETECTION/ CORRECTION CIRCUIT FEATURES SY100E193 DESCRIPTION • Hamming code generation ■ Extended 100E VEE range of –4.2V to –5.5V The SY10/100E193 are error detection and correction EDAC circuits designed for use in new, high- performance

XEP20

Abstract: SY100EPT20V SY100EPT20VZC SY100EPT20VZCTR SY10EPT20V SY10EPT20VZC SY10EPT20VZCTR
Contextual Info: Micrel, Inc. ECL Pro SY10EPT20V ECL Pro™ SY100EPT20V 5V/3.3V LVTTL/LVCMOS-to-DIFFERENTIAL LVPECL TRANSLATOR SY10EPT20V SY100EPT20V FEATURES • ■ ■ ■ ■ ■ ■ ■ 3.3V and 5V power supply options 300ps typical propagation delay Differential LVPECL output

XP33

Abstract: SY100EP33V SY100EP33VZC SY100EP33VZCTR SY10EP33V SY10EP33VKC SY10EP33VZC SY10EP33VZCTR SY100EP33VKG
Contextual Info: Micrel, Inc. Precision Edge SY10EP33V SY100EP33V Edge® 5V/3.3V 4GHz, ÷ 4 PECL/LVPECL DIVIDER SY10EP33V SY100EP33V FEATURES • Guaranteed maximum frequency >4GHz ■ 3.3V and 5V power supply options ■ Guaranteed propagation delay <460ps over

E166

Abstract: SY100E166 SY10E166 SY10E166JC
Contextual Info: 9-BIT MAGNITUDE COMPARATOR FEATURES SY10E166 SY100E166 DESCRIPTION • 1100ps max. Propagation Delay A = B ■ Extended 100E VEE range of –4.2V to –5.5V The SY10/100E166 are 9-bit magnitude comparators designed for use in new, high-performance ECL systems.

100EL01

Abstract: SY100EL01 SY100EL01ZC SY10EL01 SY10EL01ZC SY10EL01ZCTR
Contextual Info: 4-INPUT OR/NOR FEATURES • ■ ■ ■ SY10EL01 SY100EL01 DESCRIPTION 230ps propagation delay High bandwidth output transitions Internal 75KΩ input pull-down resistors Available in 8-pin SOIC package The SY10/100EL01 are 4-input OR/NOR gates. These devices are functionally equivalent to the E101 devices,

SY10E016

Abstract: MC10H016 SY100E016
Contextual Info: 8-BIT SYNCHRONOUS BINARY UP COUNTER SY10E016 SY100E016 DESCRIPTION FEATURES • ■ ■ ■ ■ ■ ■ ■ The SY10/100E016 are high-speed synchronous, presettable and cascadable 8-bit binary counters designed for use in new, high-performance ECL systems. Architecture

10EL33

Abstract: SY10EL33LZC 100EL33 el-33
Contextual Info: ClockWorks SY10EL33/L SY100EL33/L 5V/3.3V ÷ 4 DIVIDER DESCRIPTION FEATURES • ■ ■ ■ ■ ■ The SY10/100EL33/L are integrated ÷4 dividers. The differential clock inputs and the VBB allow a differential, single-ended or AC-coupled interface to the device. If

100EL04

Abstract: e104 SY100EL04 SY100EL04ZC SY10EL04 SY10EL04ZC SY10EL04ZCTR
Contextual Info: 2-INPUT AND/NAND FEATURES • ■ ■ ■ SY10EL04 SY100EL04 DESCRIPTION 240ps propagation delay High bandwidth output transitions Internal 75KΩ input pull-down resistors Available in 8-pin SOIC package The SY10/100EL04 are 2-input AND/NAND gates. These devices are functionally equivalent to the E104

ELT25

Abstract: SY100ELT25 SY100ELT25ZC SY100ELT25ZCTR
Contextual Info: DIFFERENTIAL ECL-to-TTL TRANSLATOR FEATURES • ■ ■ ■ ■ SY100ELT25 DESCRIPTION 2.6ns typical propagation delay Differential ECL inputs 24mA TTL outputs Flow-through pinouts Available in 8-pin SOIC package The SY100ELT25 is a differential ECL-to-TTL