MNA34 Search Results

NA32

Contextual Info: Multi-Layer Ceramic Chip Capacitor Array MNA Series Two or four multi-layer ceramic chip capacitors are fabricated on a single chip. Good solderability and small foot print reduce cost and space. #Dim enslons list Unit : mm MNA24 MNA22 Part No. MNA32 MNA34

MARKING V7 6-PIN

Contextual Info: 74LVC3G14 Triple inverting Schmitt trigger with 5 V tolerant input Rev. 11 — 6 July 2012 Product data sheet 1. General description The 74LVC3G14 provides three inverting buffers with Schmitt trigger input. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.

74AHC3GU04

Abstract: 74AHC3GU04DC 74AHC3GU04DP 74AHC3GU04GM JESD22-A114E MO-187
Contextual Info: 74AHC3GU04 Inverter Rev. 03 — 26 January 2009 Product data sheet 1. General description The 74AHC3GU04 is a high-speed Si-gate CMOS device. This device provides the inverting single stage function. 2. Features • Symmetrical output impedance ■ High noise immunity

74LVC3G14

Abstract: 74LVC3G14DC 74LVC3G14DP 74LVC3G14GM 74LVC3G14GT JESD22-A114E MO-187
Contextual Info: 74LVC3G14 Triple inverting Schmitt trigger with 5 V tolerant input Rev. 07 — 12 June 2008 Product data sheet 1. General description The 74LVC3G14 provides three inverting buffers with Schmitt trigger action. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of

74AHC3G04

Abstract: 74AHC3G04DC 74AHC3G04DP 74AHCT3G04 74AHCT3G04DC 74AHCT3G04DP JESD22-A114E
Contextual Info: 74AHC3G04; 74AHCT3G04 Inverter Rev. 02 — 26 January 2009 Product data sheet 1. General description The 74AHC3G04; 74AHCT3G04 is a high-speed Si-gate CMOS device. The 74AHC3G04; 74AHCT3G04 provides three inverting buffers. 2. Features • Symmetrical output impedance

74LVC2GU04

Abstract: 74LVC2GU04GM 74LVC2GU04GV 74LVC2GU04GW
Contextual Info: 74LVC2GU04 Dual inverter Rev. 6 — 27 October 2010 Product data sheet 1. General description The 74LVC2GU04 provides two inverters. Each inverter is a single stage with unbuffered output. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of

74AUP2G14

Abstract: 74AUP2G14GF 74AUP2G14GM 74AUP2G14GW
Contextual Info: 74AUP2G14 Low-power dual Schmitt trigger inverter Rev. 3 — 22 July 2010 Product data sheet 1. General description The 74AUP2G14 provides two inverting buffers with Schmitt trigger action which accept standard input signals. They are capable of transforming slowly changing input signals

74HCU04

Abstract: 74HCu04 oscillator application note dhvqfn14 NXP 74HCU04D 74HCU04D 74HCU04DB 74HCU04N 74HCU04PW
Contextual Info: 74HCU04 Hex inverter Rev. 3 — 16 September 2010 Product data sheet 1. General description The 74HCU04 is high-speed Si-gate CMOS devices and is pin compatible with low power Schottky TTL LSTTL . It is specified in compliance with JEDEC standard No. 7A.

74ALVC04

Abstract: 74ALVC04D 74ALVC04PW TSSOP14
Contextual Info: INTEGRATED CIRCUITS DATA SHEET 74ALVC04 Hex inverter Product specification 2003 Feb 04 Philips Semiconductors Product specification Hex inverter 74ALVC04 FEATURES DESCRIPTION • Wide supply voltage range form 1.65 to 3.6 V The 74ALVC04 is a high-performance, low-power,

74LVC2GU04GW

Abstract: dual inverter high power DC inverter sot363 74LVC2GU04 74LVC2GU04GV MNA053 U043
Contextual Info: INTEGRATED CIRCUITS DATA SHEET 74LVC2GU04 Dual inverter Product specification Supersedes data of 2003 Aug 29 2004 May 24 Philips Semiconductors Product specification Dual inverter 74LVC2GU04 FEATURES DESCRIPTION • Wide supply voltage range from 1.65 V to 5.5 V

74LVC2GU04

Abstract: 74LVC2GU04GM 74LVC2GU04GV 74LVC2GU04GW sot363 marking DATE code
Contextual Info: 74LVC2GU04 Dual inverter Rev. 05 — 27 October 2009 Product data sheet 1. General description The 74LVC2GU04 provides two inverters. Each inverter is a single stage with unbuffered output. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of

Contextual Info: 74AUP2G14 Low-power dual Schmitt trigger inverter Rev. 4 — 1 December 2011 Product data sheet 1. General description The 74AUP2G14 provides two inverting buffers with Schmitt trigger action which accept standard input signals. They are capable of transforming slowly changing input signals

74LVC14A-Q100

Contextual Info: 74LVC14A-Q100 Hex inverting Schmitt trigger with 5 V tolerant input Rev. 1 — 7 August 2012 Product data sheet 1. General description The 74LVC14A-Q100 provides six inverting buffers with Schmitt trigger input. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output

74LV14N

Contextual Info: 74LV14 Hex inverting Schmitt trigger Rev. 6 — 12 December 2011 Product data sheet 1. General description The 74LV14 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC14 and 74HCT14. The 74LV14 provides six inverting buffers with Schmitt-trigger input. It is capable of

74AUP2G14

Abstract: 74AUP2G14GF 74AUP2G14GM 74AUP2G14GW JESD22-A114E
Contextual Info: 74AUP2G14 Low-power dual Schmitt trigger inverter Rev. 02 — 3 July 2009 Product data sheet 1. General description The 74AUP2G14 provides two inverting buffers with Schmitt trigger action which accept standard input signals. They are capable of transforming slowly changing input signals

Contextual Info: 74AUP2G14 Low-power dual Schmitt trigger inverter Rev. 4 — 1 December 2011 Product data sheet 1. General description The 74AUP2G14 provides two inverting buffers with Schmitt trigger action which accept standard input signals. They are capable of transforming slowly changing input signals

Contextual Info: 74HC04; 74HCT04 Hex inverter Rev. 4 — 3 August 2012 Product data sheet 1. General description The 74HC04; 74HCT04 is a hex inverter. The inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.

Contextual Info: 74LVC3G04 Triple inverter Rev. 10 — 14 June 2012 Product data sheet 1. General description The 74LVC3G04 provides three inverting buffers. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.

Contextual Info: 74LVC3GU04 Triple inverter Rev. 10 — 6 July 2012 Product data sheet 1. General description The 74LVC3GU04 provides three inverters. Each inverter is a single stage with unbuffered output. Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of

74HCu04 oscillator application note

Abstract: 74HCU04 74hcu04 92s311
Contextual Info: 74HCU04 Hex inverter Rev. 4 — 12 December 2011 Product data sheet 1. General description The 74HCU04 is high-speed Si-gate CMOS devices and is pin compatible with low power Schottky TTL LSTTL . It is specified in compliance with JEDEC standard No. 7A. The 74HCU04 is a general purpose hex inverter. Each of the six inverters is a single

Contextual Info: 74LVC3G14 Triple inverting Schmitt trigger with 5 V tolerant input Rev. 12 — 9 April 2013 Product data sheet 1. General description The 74LVC3G14 provides three inverting buffers with Schmitt trigger input. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.

Contextual Info: 74AUP3G04 Low-power triple inverter Rev. 7 — 29 January 2013 Product data sheet 1. General description The 74AUP3G04 provides a low-power, low-voltage triple inverting buffer. Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall

74AHC3G14

Abstract: 74AHC3G14DP 74AHCT3G14 74AHCT3G14DP AHC3G14
Contextual Info: INTEGRATED CIRCUITS DATA SHEET 74AHC3G14; 74AHCT3G14 Inverting Schmitt trigger Product specification 2003 Nov 27 Philips Semiconductors Product specification Inverting Schmitt trigger 74AHC3G14; 74AHCT3G14 FEATURES APPLICATIONS • Symmetrical output impedance

DHVQFN14

Abstract: 74AHCU04 74AHCU04BQ 74AHCU04D 74AHCU04PW JESD22-A114E TSSOP14
Contextual Info: 74AHCU04 Hex inverter Rev. 03 — 14 November 2007 Product data sheet 1. General description The 74AHCU04 is high-speed Si-gate CMOS devices and is pin compatible with low power Schottky TTL LSTTL . It is specified in compliance with JEDEC standard No. 7A.