MNA22 Search Results
MNA22 Price and Stock
METZ CONNECT USA 142MNA22010M12 SENSOR/ACTUATOR CABLE, A-COD |
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142MNA22010 | Bulk | 1 |
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METZ CONNECT USA 142MNA22100M12 SENSOR/ACTUATOR CABLE, A-COD |
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142MNA22100 | Bulk | 1 |
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METZ CONNECT USA 142MNA22020M12 SENSOR/ACTUATOR CABLE, A-COD |
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142MNA22020 | Bulk | 1 |
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METZ CONNECT USA 142MNA22050M12 SENSOR/ACTUATOR CABLE, A-COD |
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142MNA22050 | Bulk | 1 |
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MNA22 Datasheets Context Search
Catalog Datasheet | Type | Document Tags | |
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NA32Contextual Info: Multi-Layer Ceramic Chip Capacitor Array MNA Series Two or four multi-layer ceramic chip capacitors are fabricated on a single chip. Good solderability and small foot print reduce cost and space. #Dim enslons list Unit : mm MNA24 MNA22 Part No. MNA32 MNA34 |
OCR Scan |
MNA22 MNA24 MNA32 MNA34 A22/M A24/M MNA34 178mm NA32 | |
dhvqfn14
Abstract: 74AHCT08D NXP 74AHC08 74AHC08BQ 74AHC08D 74AHC08PW 74AHCT08 74AHCT08D 74AHCT08PW JESD22-A114E
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74AHC08; 74AHCT08 74AHCT08 74AHC08 JESD22-A114E JESD22-A115-A dhvqfn14 74AHCT08D NXP 74AHC08BQ 74AHC08D 74AHC08PW 74AHCT08D 74AHCT08PW | |
Contextual Info: 74LVC1G08 Single 2-input AND gate Rev. 9 — 9 December 2011 Product Specification 1. General description The 74LVC1G08 provides one 2-input AND function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications. |
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74LVC1G08 74LVC1G08 771-LVC1G08GWDG125 74LVC1G08GW/DG | |
74AHC2G08
Abstract: 74AHC2G08DC 74AHC2G08DP 74AHCT2G08 74AHCT2G08DC 74AHCT2G08DP JESD22-A114E
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74AHC2G08; 74AHCT2G08 74AHCT2G08 JESD22-A114E JESD22-A115-A JESD22-C101C 74AHC2G08DP 74AHC2G08 74AHC2G08DC 74AHC2G08DP 74AHCT2G08DC 74AHCT2G08DP | |
21A1
Abstract: 74LV125DB 74HC125 74HCT125 74LV125 74LV125D 74LV125N 74LV125PW JESD22-A114E
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74LV125 74LV125 74HC125 74HCT125. 21A1 74LV125DB 74HCT125 74LV125D 74LV125N 74LV125PW JESD22-A114E | |
AHCT32
Abstract: 74AHC32 74AHC32BQ 74AHC32D 74AHC32PW 74AHCT32 TSSOP14
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74AHC32; 74AHCT32 74AHCT32 74AHC32: 74AHCT32: EIA/JESD22-A114E EIA/JESD22-A115-A AHCT32 74AHC32 74AHC32BQ 74AHC32D 74AHC32PW TSSOP14 | |
74AUP2G125
Abstract: 74AUP2G125DC 74AUP2G125GT JESD22-A114E JESD78
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74AUP2G125 74AUP2G125 74AUP2G125DC 74AUP2G125GT JESD22-A114E JESD78 | |
74LVC2G86
Abstract: 74LVC2G86DC 74LVC2G86DP 74LVC2G86GM 74LVC2G86GT
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74LVC2G86 74LVC2G86 74LVC2G86DC 74LVC2G86DP 74LVC2G86GM 74LVC2G86GT | |
74LVC2G32
Abstract: 74LVC2G32DC 74LVC2G32DP 74LVC2G32GM 74LVC2G32GT XSON8 SOT1116
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74LVC2G32 74LVC2G32 74LVC2G32DC 74LVC2G32DP 74LVC2G32GM 74LVC2G32GT XSON8 SOT1116 | |
74LVC2G32
Abstract: 74LVC2G32DC 74LVC2G32DP 74LVC2G32GM 74LVC2G32GT MO-187 VSSOP8
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74LVC2G32 74LVC2G32 74LVC2G32DC 74LVC2G32DP 74LVC2G32GM 74LVC2G32GT MO-187 VSSOP8 | |
74ALVC125
Abstract: 74ALVC125D 74ALVC125PW TSSOP14
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74ALVC125 74ALVC125 JESD8B/JESD36 SCA74 613508/01/pp16 74ALVC125D 74ALVC125PW TSSOP14 | |
Contextual Info: 74AHC2G32; 74AHCT2G32 Dual 2-input OR gate Rev. 01 — 23 February 2004 Product data sheet 1. General description The 74AHC2G/AHCT2G32 is a high-speed Si-gate CMOS device. This device provides two 2-input OR gates. 2. Features • Symmetrical output impedance |
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74AHC2G32; 74AHCT2G32 74AHC2G/AHCT2G32 EIA/JESD22-A114-A EIA/JESD22-A115-A EIA/JESD22-C101 OT505-2 OT765-1 | |
Contextual Info: 74AUP2G08 Low-power dual 2-input AND gate Rev. 5 — 1 December 2011 Product data sheet 1. General description The 74AUP2G08 provides the dual 2-input AND function. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall |
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74AUP2G08 74AUP2G08 | |
Contextual Info: 74AUP1G08 Low-power 2-input AND gate Rev. 4 — 15 November 2011 Product data sheet 1. General description The 74AUP1G08 provides the single 2-input AND function. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall |
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74AUP1G08 74AUP1G08 | |
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Contextual Info: 74LVC08A Quad 2-input AND gate Rev. 6 — 16 December 2011 Product data sheet 1. General description The 74LVC08A provides four 2-input AND gates. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications. |
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74LVC08A 74LVC08A JESD8-C/JESD36 JESD22-A114F JESD22-A115-B JESD22-C101E | |
Contextual Info: 74LV86 Quad 2-input exclusive-OR gate Rev. 03 — 27 November 2007 Product data sheet 1. General description The 74LV86 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC86 and 74HCT86. The 74LV86 provides a quad 2-input exclusive-OR function. |
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74LV86 74LV86 74HC86 74HCT86. JESD22-A114E JESD22-A115-A | |
74LVC125A
Abstract: 74LVC125AD 74LVC125ADB 74LVC125APW
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74LVC125A 74LVC125A SCA74 613508/03/pp16 74LVC125AD 74LVC125ADB 74LVC125APW | |
74HC08
Abstract: 74HCT08 74HC08D 74HC08DB 74HC08N 74HCT08D 74HCT08N 74HC08PW
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74HC08; 74HCT08 74HC/HCT08 EIA/JESD22-A114-A EIA/JESD22-A115-A 74HC08 OT402-1 MO-153 74HC08 74HCT08 74HC08D 74HC08DB 74HC08N 74HCT08D 74HCT08N 74HC08PW | |
MNA220
Abstract: 74ALVC08 74ALVC08BQ 74ALVC08D 74ALVC08PW DHVQFN14 TSSOP14 JESD87
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74ALVC08 74ALVC08 JESD8B/JESD36 OT108-1 076E06 MS-012 MNA220 74ALVC08BQ 74ALVC08D 74ALVC08PW DHVQFN14 TSSOP14 JESD87 | |
11851
Abstract: 74LVC2G86 74LVC2G86DP
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74LVC2G86 74LVC2G86 SCA75 R20/01/pp12 11851 74LVC2G86DP | |
Contextual Info: 74AHC2G32; 74AHCT2G32 Dual 2-input OR gate Rev. 3 — 14 May 2013 Product data sheet 1. General description The 74AHC2G32; 74AHCT2G32 is a high-speed Si-gate CMOS device. The 74AHC2G32; 74AHCT2G32 provides two 2-input OR gates. 2. Features and benefits Symmetrical output impedance |
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74AHC2G32; 74AHCT2G32 74AHCT2G32 JESD22-A114E JESD22-A115-A JESD22-C101C 74AHC2G32DP | |
ESD 141Contextual Info: 74AUP2G125 Low-power dual buffer/line driver; 3-state Rev. 10 — 8 February 2013 Product data sheet 1. General description The 74AUP2G125 provides the dual non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input nOE . A HIGH level at pin nOE |
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74AUP2G125 74AUP2G125 ESD 141 | |
Contextual Info: 74LVC125A Quad buffer/line driver with 5 V tolerant input/outputs; 3-state Rev. 5 — 8 February 2012 Product data sheet 1. General description The 74LVC125A consists of four non-inverting buffers/line drivers with 3-state outputs nY that are controlled by the output enable input (nOE). A HIGH at nOE causes the |
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74LVC125A 74LVC125A JESD8-B/JESD36 | |
74LVC1G08GV
Abstract: 74LVC1G08 74LVC1G08GM 74LVC1G08GW
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74LVC1G08 74LVC1G08 JESD8B/JESD36 SCA76 R20/05/pp15 74LVC1G08GV 74LVC1G08GM 74LVC1G08GW |