DS102 Search Results

4032V

Abstract: DS1017 LC4032V-10TN48I 4512c application LC4256V-75TN176C marking 17Z 4000B AEC-Q100 DS1020 22z2
Contextual Info: ispMACH 4000V/B/C/Z Family 3.3V/2.5V/1.8V In-System Programmable SuperFAST TM High Density PLDs Coolest Power May 2009 C Features Data Sheet DS1020 TM • Broad Device Offering • Multiple temperature range support – Commercial: 0 to 90°C junction Tj

74F04

Abstract: DS1021 DS1021-25 DS1021-50 DS1021S
Contextual Info: DS1021 nAI I A S DS1021 s e m ic o n d u c t o r Programmable 8-Bit Silicon Delay Line FEATURES PIN ASSIGNMENT • All-silicon time delay C C C 1 16 2 15 H H 3 14 1 s pi c 4 13 P2 C C C C 5 12 6 11 7 10 8 9 IN • Models with 0.25 ns and 0.5 ns steps E Q/PO

74F04

Abstract: DS1020 DS1020-100 DS1020-15 DS1020-200 DS1020-25 DS1020-50 DS1020S
Contextual Info: DS1020 DALLAS s e m ic o n d u c t o r DS1020 Programmable 8-Bit Silicon Delay Line FEATURES PIN ASSIGNMENT • All-silicon tim e delay IN • Models with 0.15 ns, 0.25 ns, 0.5 ns, 1 ns, and 2 ns steps 16 ] VCC 2 15 ] OUT Q/PO 3 14 ] P1 4 13 P2 5 12 E • Program m able using 3-wire serial port or 8-bit parallel

16-PIN

Abstract: delay line 16PIN DS1023-500 DS1023 DS1023-100 DS1023S-500 300MIL DS1023-050 DS1023S-025
Contextual Info: PROGRAMMABLE DELAY LINE HAS 4x IMPROVEMENT IN INTEGRAL LINEARITY DS1023 8-Bit Silicon Delay Line Supports Serial or Parallel Programming The DS1023 programmable delay line, a DS1020/21 upgrade, allows for processor control of signal timing delays via either a 3-wire serial or 8-bit parallel port. The DS1023 is the first programmable delay line to allow

DS1425L-F5

Abstract: rtc ds1307 dallas ds2501 dallas ds2501 Datasheet dallas ds1280 DS2501 ds1642-150 DS1669 replacement ds2501 Datasheet DS1608S
Contextual Info: ORDERING INFORMATION DEVICE DS0621–SDK DS0630 DS1000 DS1000–IND DS1003 DS1004 DS1005 DS1007 DS1010 DS1012 DS1013 DS1020 DS1021 DS1033 DS1035 DS1040 PACKAGE TYPE Software Software 14–Pin DIP 8–Pin DIP 16–Pin SOIC 8–Pin SOIC 8–Pin DIP 8–Pin SOIC

Contextual Info: Rev 1; 4/09 5.0V 8-Bit Programmable Timing Element Features The DS1124 is an 8-bit programmable timing element similar in function to the DS1021-25. The 256-delay intervals are programmed by using a 3-wire serial interface. With a 0.25ns step size, the DS1124 can provide

Contextual Info: LatticeECP3 Family Data Sheet DS1021 Version 02.1EA, February 2012 LatticeECP3 Family Data Sheet Introduction February 2012 Data Sheet DS1021 Features • Dedicated read/write levelling functionality • Dedicated gearing logic • Source synchronous standards support

Contextual Info: ispMACH 4000V/B/C/Z Family 3.3V/2.5V/1.8V In-System Programmable SuperFAST TM High Density PLDs November 2013 Data Sheet DS1020  Broad Device Offering Features • Multiple temperature range support – Commercial: 0 to 90°C junction Tj – Industrial: -40 to 105°C junction (Tj)

Contextual Info: ispMACH 4000ZE Family 1.8V In-System Programmable Ultra Low Power PLDs August 2013 Data Sheet DS1022  Broad Device Offering Features • 32 to 256 macrocells • Multiple temperature range support – Commercial: 0 to 90°C junction Tj – Industrial: -40 to 105°C junction (Tj)

Contextual Info: DS1023 8-Bit Programmable Timing Element www.maxim-ic.com PIN ASSIGNMENT FEATURES § § § § § § § § Step sizes of 0.25 ns, 0.5 ns, 1 ns, 2 ns, 5 ns On-chip reference delay Configurable as delay line, pulse width modulator, or free-running oscillator

LFE3-17EA

Abstract: LFE3-35EA-6FN484C DS1021 ECP3-35 ECP3-95 16x4-Bit convolution encoders LFE335EA6FN484C LFE3-35EA-8FN484C LFE3-95EA-6FN484C
Contextual Info: LatticeECP3 Family Data Sheet DS1021 Version 01.9EA, July 2011 LatticeECP3 Family Data Sheet Introduction December 2010 Data Sheet DS1021 Features • Dedicated read/write levelling functionality • Dedicated gearing logic • Source synchronous standards support

Contextual Info: ispMACH 4000V/B/C/Z Family 3.3V/2.5V/1.8V In-System Programmable SuperFAST TM High Density PLDs Coolest Power November 2007 C Features Data Sheet DS1020 TM • Broad Device Offering • Multiple temperature range support – Commercial: 0 to 90°C junction Tj

DS1023-025

Abstract: DS1023-200 pulse width measure counter delay clock DS1023 DS1023-100 DS1023-25 DS1023-50 DS1023-500 DS1023S
Contextual Info: DS1023 DALLAS s e m ic o n d u c to r DS1023 8 -B it Programmable Timing Element FEATURES PIN ASSIGNMENT E E E E E E E E IN • O n -c h ip R eference delay LE • C onfigurable as Delay Line, Pulse W idth Modulator, or Free-runn ing O scillator Q/P0 CLK/P1

Contextual Info: LatticeECP3 Family Data Sheet DS1021 Version 02.5EA, February 2014 LatticeECP3 Family Data Sheet Introduction February 2012 Data Sheet DS1021 Features • Dedicated read/write levelling functionality • Dedicated gearing logic • Source synchronous standards support

Lattice ispmach LC4064V

Abstract: LC4064V75TN100C LC4064V LC4128V-75TN100C ispMACH lc4064v LC4128V-27TN100C LC4064V-75TN48C Lc4064v pinout 132csBGA LC4032V-75TN48C
Contextual Info: ispMACH 4000V/B/C/Z Family 3.3V/2.5V/1.8V In-System Programmable SuperFAST TM High Density PLDs Coolest Power C Features Data Sheet DS1020 TM • Broad Device Offering • Multiple temperature range support – Commercial: 0 to 90°C junction Tj – Industrial: -40 to 105°C junction (Tj)

lc4032ze

Abstract: LC4128ZE-5T100C lc4032ze-7tn48c LC4032ZE-5MN64I LC4032ZE-7TN48I LC4256ZE-7TN144C 4032ZE LC4064ZE7TN100C LC4128ZE-7TN100C LC4064ZE-7TN48C
Contextual Info: ispMACH 4000ZE Family 1.8V In-System Programmable Ultra Low Power PLDs April 2008 Advance Data Sheet DS1022 • Broad Device Offering Features • 32 to 256 macrocells • Multiple temperature range support – Commercial: 0 to 90°C junction Tj – Industrial: -40 to 105°C junction (Tj)

Contextual Info: LA-LatticeXP2 Family Data Sheet DS1024 Version 01.3, January 2012 LA-LatticeXP2 Family Data Sheet Introduction January 2012 Data Sheet DS1024 Features  Flexible I/O Buffer • sysIO buffer supports: – LVCMOS 33/25/18/15/12; LVTTL – SSTL 33/25/18 class I, II

DS1020-015

Abstract: distance measure ultrasonic
Contextual Info: Application Note 107 DS1020/DS1021 8-Bit Programmable Delay Lines www.dalsemi.com INTRODUCTION This application note is designed to assist in the use of the DS1020/DS1021 programmable delay lines. The basic principles of device operation are covered in simplified form, but with sufficient detail to

Contextual Info: DALLAS SEMICONDUCTOR DS1021 Programmable 8-Bit Silicon Delay Line PIN ASSIGNMENT FEATURES • All-silicon time delay c 16 15 : OUT Q/PO c 3 14 S P1 c 4 13 : 12 : P7 11 : 10 C E c • Programmable using 3-wire serial port or 8-bit part llel port P2 c P3 c • Leading and trailing edge accuracy

l37c 8 pin

Abstract: L41C G40TL l34c L43C L74c L18T l14c L25C ENCODER l31c
Contextual Info: ORCA ORT42G5 and ORT82G5 0.6 to 3.7 Gbps XAUI and FC FPSCs July 2008 Data Sheet DS1027 Introduction Lattice Semiconductor has developed a family of next generation FPSCs intended for high-speed serial backplane data transmission. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the

LAXP2-5E-5TN144E

Abstract: DS1024 TN1137 AEC-Q100 turbo encoder simulink QNEG01
Contextual Info: LA-LatticeXP2 Family Data Sheet DS1024 Version 01.1, August 2008 LA-LatticeXP2 Family Data Sheet Introduction June 2008 Data Sheet DS1024 • Flexible I/O Buffer Features • sysIO buffer supports: – LVCMOS 33/25/18/15/12; LVTTL – SSTL 33/25/18 class I, II

ECP3EA

Abstract: LFE3-95EA-6FN484C Socket 1156 VID pinout DDR3 timing lfe3-17ea-6fn484c lfe3 LFE3-17EA6FN484C
Contextual Info: LatticeECP3 Family Data Sheet DS1021 Version 02.2EA, April 2012 LatticeECP3 Family Data Sheet Introduction February 2012 Data Sheet DS1021 Features • Dedicated read/write levelling functionality • Dedicated gearing logic • Source synchronous standards support

Contextual Info: SE C E U DA L R a T R A tt EN S ic e T HE EC IN E P FO T 3 F R O EA M R A TI O N LatticeECP3 Family Data Sheet Preliminary DS1021 Version 01.6, March 2010 LatticeECP3 Family Data Sheet Introduction November 2009 Preliminary Data Sheet DS1021 Features • Dedicated read/write levelling functionality

10KW

Abstract: 74F04 DS1021 DS1021S
Contextual Info: DS1021 DS1021 Programmable 8-Bit Silicon Delay Line FEATURES PIN ASSIGNMENT • All-silicon time delay • Models with 0.25 ns and 0.5 ns steps • Programmable using 3-wire serial port or 8-bit parallel port IN 1 16 VCC E Q/PO 2 15 OUT 3 14 S P1 4 5 13 12