DS1021 Search Results

74F04

Abstract: DS1021 DS1021-25 DS1021-50 DS1021S
Contextual Info: DS1021 nAI I A S DS1021 s e m ic o n d u c t o r Programmable 8-Bit Silicon Delay Line FEATURES PIN ASSIGNMENT • All-silicon time delay C C C 1 16 2 15 H H 3 14 1 s pi c 4 13 P2 C C C C 5 12 6 11 7 10 8 9 IN • Models with 0.25 ns and 0.5 ns steps E Q/PO

DS1425L-F5

Abstract: rtc ds1307 dallas ds2501 dallas ds2501 Datasheet dallas ds1280 DS2501 ds1642-150 DS1669 replacement ds2501 Datasheet DS1608S
Contextual Info: ORDERING INFORMATION DEVICE DS0621–SDK DS0630 DS1000 DS1000–IND DS1003 DS1004 DS1005 DS1007 DS1010 DS1012 DS1013 DS1020 DS1021 DS1033 DS1035 DS1040 PACKAGE TYPE Software Software 14–Pin DIP 8–Pin DIP 16–Pin SOIC 8–Pin SOIC 8–Pin DIP 8–Pin SOIC

Contextual Info: Rev 1; 4/09 5.0V 8-Bit Programmable Timing Element Features The DS1124 is an 8-bit programmable timing element similar in function to the DS1021-25. The 256-delay intervals are programmed by using a 3-wire serial interface. With a 0.25ns step size, the DS1124 can provide

Contextual Info: LatticeECP3 Family Data Sheet DS1021 Version 02.1EA, February 2012 LatticeECP3 Family Data Sheet Introduction February 2012 Data Sheet DS1021 Features • Dedicated read/write levelling functionality • Dedicated gearing logic • Source synchronous standards support

LFE3-17EA

Abstract: LFE3-35EA-6FN484C DS1021 ECP3-35 ECP3-95 16x4-Bit convolution encoders LFE335EA6FN484C LFE3-35EA-8FN484C LFE3-95EA-6FN484C
Contextual Info: LatticeECP3 Family Data Sheet DS1021 Version 01.9EA, July 2011 LatticeECP3 Family Data Sheet Introduction December 2010 Data Sheet DS1021 Features • Dedicated read/write levelling functionality • Dedicated gearing logic • Source synchronous standards support

Contextual Info: LatticeECP3 Family Data Sheet DS1021 Version 02.5EA, February 2014 LatticeECP3 Family Data Sheet Introduction February 2012 Data Sheet DS1021 Features • Dedicated read/write levelling functionality • Dedicated gearing logic • Source synchronous standards support

DS1020-015

Abstract: distance measure ultrasonic
Contextual Info: Application Note 107 DS1020/DS1021 8-Bit Programmable Delay Lines www.dalsemi.com INTRODUCTION This application note is designed to assist in the use of the DS1020/DS1021 programmable delay lines. The basic principles of device operation are covered in simplified form, but with sufficient detail to

Contextual Info: DALLAS SEMICONDUCTOR DS1021 Programmable 8-Bit Silicon Delay Line PIN ASSIGNMENT FEATURES • All-silicon time delay c 16 15 : OUT Q/PO c 3 14 S P1 c 4 13 : 12 : P7 11 : 10 C E c • Programmable using 3-wire serial port or 8-bit part llel port P2 c P3 c • Leading and trailing edge accuracy

ECP3EA

Abstract: LFE3-95EA-6FN484C Socket 1156 VID pinout DDR3 timing lfe3-17ea-6fn484c lfe3 LFE3-17EA6FN484C
Contextual Info: LatticeECP3 Family Data Sheet DS1021 Version 02.2EA, April 2012 LatticeECP3 Family Data Sheet Introduction February 2012 Data Sheet DS1021 Features • Dedicated read/write levelling functionality • Dedicated gearing logic • Source synchronous standards support

Contextual Info: SE C E U DA L R a T R A tt EN S ic e T HE EC IN E P FO T 3 F R O EA M R A TI O N LatticeECP3 Family Data Sheet Preliminary DS1021 Version 01.6, March 2010 LatticeECP3 Family Data Sheet Introduction November 2009 Preliminary Data Sheet DS1021 Features • Dedicated read/write levelling functionality

10KW

Abstract: 74F04 DS1021 DS1021S
Contextual Info: DS1021 DS1021 Programmable 8-Bit Silicon Delay Line FEATURES PIN ASSIGNMENT • All-silicon time delay • Models with 0.25 ns and 0.5 ns steps • Programmable using 3-wire serial port or 8-bit parallel port IN 1 16 VCC E Q/PO 2 15 OUT 3 14 S P1 4 5 13 12

me 102

Contextual Info: DS1 02 1 DALLAS SEMICONDUCTOR DS1021 Program m able 8-Bit Silicon Delay Line FEA TU R E S PIN A S S IG N M E N T • A l l- s i l ic o n t i m e d e l a y IN • M o d e l s wit h 0 . 2 5 n s a n d 0 .5 ns s t e p s E Q iP O • P r o g r a m m a b l e u s in g 3 - w i r e s e r ia l p o r t o r 8 - b i t p a r a l le l

Contextual Info: DS1021 D ALLAS s e m ic o n d u c to r DS1021 Programmable 8-Bit Silicon Delay Line FEATURES PIN ASSIGNMENT • All-silicon time delay • Models with 0.25 ns and 0.5 ns steps • Program m ableusing 3-wire serial port o r8 -b it parallel port • Leading and trailing edge accuracy

Contextual Info: Rev 1; 4/09 5.0V 8-Bit Programmable Timing Element Features The DS1124 is an 8-bit programmable timing element similar in function to the DS1021-25. The 256-delay intervals are programmed by using a 3-wire serial interface. With a 0.25ns step size, the DS1124 can provide

DS1020

Abstract: DS1020-025 DS1020-050 DS1020-100 DS1020-200 DS1021 ultrasonic rangefinder notes APP-107 DS1020-015
Contextual Info: Maxim > App Notes > OSCILLATORS/DELAY LINES/TIMERS/COUNTERS Keywords: delay lines, programmable delay line, DS1020, DS1021 Mar 29, 2001 APPLICATION NOTE 107 DS1020/DS1021 8-Bit Programmable Delay Lines Abstract: This application note is designed to assist in the use of the DS1020/DS1021 programmable delay

Contextual Info: LatticeECP3 Family Data Sheet DS1021 Version 02.6EA, March 2014 LatticeECP3 Family Data Sheet Introduction February 2012 Data Sheet DS1021 Features • Dedicated read/write levelling functionality • Dedicated gearing logic • Source synchronous standards support

Contextual Info: LatticeECP3 Family Data Sheet Preliminary DS1021 Version 01.6, March 2010 LatticeECP3 Family Data Sheet Introduction November 2009 Preliminary Data Sheet DS1021 Features • Dedicated read/write levelling functionality • Dedicated gearing logic • Source synchronous standards support

Contextual Info: LatticeECP3 Family Data Sheet DS1021 Version 02.7EA, April 2014 LatticeECP3 Family Data Sheet Introduction February 2012 Data Sheet DS1021 Features • Dedicated read/write levelling functionality • Dedicated gearing logic • Source synchronous standards support

LFE3-150EA-8FN1156C

Abstract: LFE3-70EA-6FN672C lfe3-17ea-6fn484c lfe3 LFE3-17EA6FN484C LFE3-17EA
Contextual Info: LatticeECP3 Family Data Sheet DS1021 Version 02.0EA, November 2011 LatticeECP3 Family Data Sheet Introduction November 2011 Data Sheet DS1021 Features • Dedicated read/write levelling functionality • Dedicated gearing logic • Source synchronous standards support

AN-977

Abstract: AN977 APP977 DS1020 DS1021 DS1023 DS1040 DS1100 DS1110 DS1135
Contextual Info: Maxim > App Notes > OSCILLATORS/DELAY LINES/TIMERS/COUNTERS Keywords: delay lines, one-shot, pulse-width modulator, PWM, DS1100, DS1135, DS1110, DS1020, DS1021, DS1023, DS1123 Feb 22, 2002 APPLICATION NOTE 977 Tech Brief 34: Building Precision Pulse Width Modulators Using

DS1669-100

Abstract: TQFP 100 pin Socket 4 pin dip switch DS2401 PACKAGE 16 pin DIP socket DS1804 NV 2 pin dip switch ds1232(ind) data sheet ds1642-150 DS1620S
Contextual Info: ORDERING INFORMATION DEVICE DS0621–SDK DS1000 DS1000–IND DS1003 DS1004 DS1005 DS1007 DS1010 DS1012 DS1013 DS1020 DS1021 DS1033 DS1035 DS1040 PACKAGE TYPE Software 14–Pin DIP 8–Pin DIP 16–Pin SOIC 8–Pin SOIC 8–Pin DIP 8–Pin SOIC 14–Pin DIP

DS1021-25

Abstract: DS1124 TD255
Contextual Info: Rev 0; 7/07 5.0V 8-Bit Programmable Timing Element Features The DS1124 is an 8-bit programmable timing element similar in function to the DS1021-25. The 256-delay intervals are programmed by using a 3-wire serial interface. With a 0.25ns step size, the DS1124 can provide

Contextual Info: DS1021 DALLAS SEMICONDUCTOR DS1021 Programmable 8-Bit Silicon Delay Line FEATURES PIN ASSIGNMENT • All-silicon time delay IN C 1 16 c 2 15 Q/PO c 3 14 □ s c 4 5 13 P7 P2 L 12 n P6 P3 L 6 11 C P4 c 7 10 • Economical GND c 8 9 • Auto-insertable, low profile, 16-pin SOIC package

LFE3-17EA

Abstract: DS1021 ECP3-35 ECP3-95 LFE3-17EA-7FN484C lfe370e6fn672i LFE3-70EA8FN672 lfe3-70e 4420 ba LFE3-70EA-7FN484C
Contextual Info: LatticeECP3 Family Data Sheet Preliminary DS1021 Version 01.6, March 2010 LatticeECP3 Family Data Sheet Introduction November 2009 Preliminary Data Sheet DS1021 Features • Dedicated read/write levelling functionality • Dedicated gearing logic • Source synchronous standards support