BT8330 Search Results

78P7200

Abstract: CR01 CR02 CR04 CR05 CR022
Contextual Info: Bt8330 DS3/E3 Framer with 52 Mbps HDLC Controller The Bt8330 is an integral DS3/E3 framer and transceiver designed to support the transmission formats defined by ANSI T1.107-1988, T1.107a-1989, T1.404, and ITU-T G.751 standards. All maintenance features required by Bellcore

RD7AL

Contextual Info: Product Description This specification describes the Bt8330 frame synchronization, recovery, and sig­ nal generation circuit. Applications for digital terminals include digital cross-connect systems, customer premise multiplexers, channel extenders, network

Contextual Info: llOii Product Description - This specification describes the Bt8330 frame synchronization, recovery, and sig­ nal generation circuit. Applications for digital terminals include digital cross-con­ nect systems, customer premise multiplexers, channel extenders, network

tms 3874

Abstract: RS8228EBG RS8398 Rockwell framer" Trec Part Numbering System GR
Contextual Info: R O C K W E L L Network access S E M I C O N D U C T O R S Y S T E M S RS8228 Octal ATM Transmission Convergence PHY Device datasheett PROVIDING HIGH SPEED MULTIMEDIA CONNECTIONS September 1998 Advance Information This document contains information on a product under development. The parametric information contains target

GG1Q

Contextual Info: 1.0 Product Description 1.1 Introduction Figure 1-1 is a detailed block diagram o f the Bt8222. For transmission from the host system, octet-wide data is input from the UTOPIA or FIFO ports. The host data is assembled into ATM cells and then formatted for serial line transmission

rsm 2814

Contextual Info: 1.0 Product Description - The Bt8209 and Bt8210 Switched Multimegabit Data Service SMDS Control and Reassembly Formatters (SCARF) provide a single-access SMDS service ter­ mination for connectionless data, “datagram,” transfer according to Bellcore TRTSV-000772 and TR-TSV-000773. Customer Premise Equipment (CPE) and

Contextual Info: 4.0 Mechanical/Electrical Specifications Table 4-1 and Figure 4-1 illustrate the timing requirements for the microprocessor interface. The parameter tcyc is the period of the receive DS3/E3 clock DS3CKI . This clock signal is used in the read circuit of the microprocessor to ensure that

SH 6770

Contextual Info: 1.0 Product Description 1.1 Overview The B t8 2 l5 is a bidirectional buffer with a 36-bit bidirectional port and 9-bit uni­ directional ports that can be configured to transfer iixed-length cells. Bach direc­ tion can store up to 512 36-bit words. This part, therefore, replaces eight

nortel CS 1500

Abstract: 1F42 QMV1025BS5 nortel cs 2000 93-001R2 1D08 QMV1025CS5 SLC96 NORTEL CPC 7415 4 -bit
Contextual Info: Lunar Data Book Publication Number: 84001.08/03-00 Issue 2 This data book applies to Lunar devices identified with the following product codes: PEC Code QMV1025BS5 CPC Code AO791373 PEC Code QMV1025CS5 (CPC Code AO799545) PROPRIETARY INFORMATION The information contained in this document is the property of Nortel Networks.

00a3r

Abstract: NORTEL CPC 1F42 motorola bipolar transistor databook st linear databook cmos logic databook ds2-s motorola cmos databook ttl databook PM4344
Contextual Info: Lunar Databook Publication Number: 84001.08/03-99 This data book applies to Lunar devices identified with the QMV1025AS5 Product Engineering Code CPC Code AO732780 PROPRIETARY INFORMATION The information contained in this document is the property of Northern Telecom. Except as

28228-11

Contextual Info: RS8228/M28228 Octal ATM Transmission Convergence PHY Device The RS8228 Octal ATM Transmission Convergence PHY device dramatically improves performance for switch and access system low-speed ports by integrating all the ATM physical layer processing functions found in the ATM Forum Cell Based Transmission

Contextual Info: 1.0 Product Description The R S8228 Octal ATM Transm ission Convergence TC PH Y device dram ati­ cally increases the level o f integration for switches and access systems. The R S8228 integrates all o f the ATM Layer processing functions found in the ATM

L8222

Abstract: OQ 051
Contextual Info: 1.0 Product Description 1.1 Introduction Figure 1-1 is a detailed block diagram of the Bt8222. For transmission from the host system, octet-wide data is input from the UTOPIA or FIFO ports. The host data is assembled into ATM cells and then formatted for serial line transmission

syn 7580

Abstract: 80960CA intel 8212 data sheet BSDE diode marking code 4n TPS 1028 1840H bicon TTL catalog Bt8215EPF
Contextual Info: Bt8215 Bidirectional Cell Buffer The Bt8215 Bidirectional Cell Buffer simplifies full-duplex communication between a 32-bit wide system bus and a 8-bit duplex peripheral bus. The buffer depth in each direction is 2048 bytes and can easily be expanded with off-theshelf FIFO parts. Special modes for buffering ATM cells are included.

HDB3 AMI ENCODER DECODER

Abstract: CN8332EXF CN8333EXF GP00-D537
Contextual Info: Advance Information This document contains information on a product under development. The parametric information contains target parameters that are subject to change. CN8332/CN8333 Dual/Triple E3/DS3/STS-1 Line Interface Unit The CN8333 is a three-channel, E3/DS3/STS-1 fully integrated Line Interface Unit LIU

"network interface cards"

Contextual Info: Advance Information This document contains information on a product under development. The parametric information contains target parameters that are subject to change. Printed exclusively for DataRace Bt8230 ATM Segmentation and Reassembly Controller—SRC

RS8228EBGB

Abstract: 28228-12 100064B
Contextual Info: RS8228 Octal ATM Transmission Convergence PHY Device The RS8228 Octal ATM Transmission Convergence PHY device dramatically improves performance for switch and access system low-speed ports by integrating all the ATM physical layer processing functions found in the ATM Forum Cell Based Transmission

Contextual Info: |OÈ\ Mechanical and Electrical Specifications w y - Table 8 and Figure 19 illustrate the timing requirements for the microprocessor interface. The parameter tcyc is the period o f the receive DS3/E3 clock DS3CKI .

Contextual Info: |p I 1.0 Product Description The Bt8230 Segmentation and Reassembly Controller SRC incorporates a host interface, Asynchronous Transfer Mode (ATM) Adaptation Layer processing, and line interfaces in a single device. This highly integrated ATM device combines

Contextual Info: Advance Information This document contains information informati on a product under development. The parametric information contains target parameters that are subject to change. » *v _ C O N E X A N T CN8332/CN8333 Dual/Triple E3/DS3/STS-1 Line Interface Unit

Contextual Info: INTERFACE SPECIFICATION BIDIRECTIONAL CELL BUFFER B t8 2 1 5 1 .0 INTRODUCTION T he B t8215 is a bidirectional buffer w ith a 36-bit bidirectional p o rt and 9 -b it unid irectio n al p o rts th at can be configured to transfer fixed-length cells. Each direction can store up to 512 3 6 -b it w ords. T his part, therefore,