AS7C31024 Search Results

Contextual Info: High Performance 128KX8 CMOS SRAM AS7C1024 AS7C31024 128KX8 CMOS SRAM Features • Organization: 131,072 words x 8 bits • High speed - 1 0 / 1 2 / 1 5 / 2 0 / 2 5 ns address access time - 3 / 3 / 4 / 5 / 6 ns output enable access time • Low power consumption

Contextual Info: $SULO##5333 $6:&4357 $6:&64357 8926169#45;.ð;#&026#65$0#+ YROXWLRQDU\#3LQRXW, HDWXUHV • AS7C1024 (5V version) • AS7C31024 (3.3V version) • Industrial and commercial temperatures • Organization: 131,072 words x 8 bits • High speed - 10/12/15/20 ns address access time

megatron

Abstract: 10N12 Beacon 406 MHz AS7C31024 BJ 919 26A41
Contextual Info: High Performance 128Kx8 3.3V CMOS SRAM H J 8 |j ^ AS7C31024 AS7C31024L PRELIMINARY _ Low Voltage 128Kx8 CMOS SRAM Common I/O FEATURES • Organization: 131,072 words x 8 bits • Equal access and cycle times • Single 3.3 ±0.3V power supply

Collins Electronics

Abstract: lm 3751 AS7010 NT 407 F 0637 Z05 AS7C1024-20PC LR 3441 AS7C1024 AS7C31024 AS701024-12TJC
Contextual Info: H ig h P e r f o r m a n c e 128KX8 C M O S SR A M A AS7C1024 AS7C31024 128KX8 CMOS SRAM Features • Organization: 131,072 words x 8 bits • High speed - 1 0 / 1 2 / 1 5 / 2 0 / 2 5 ns address access time - 3 / 3 / 4 / 5 / 6 n s output enable access time

AS7C1024-15TI

Abstract: AS7C1024 AS7C1024-10 AS7C1024-12 AS7C1024-15 AS7C1024-20 AS7C31024 AS7C31024-10 AS7C31024-12 AS7C31024-15
Contextual Info: November 2000 AS7C1024 AS7C31024 5V/3.3V 128Kx8 CMOS SRAM Evolutionary Pinout Features • 2.0V data retention • Easy memory expansion with CE1, CE2, OE inputs • TTL/LVTTL-compatible, three-state I/O • 32-pin JEDEC standard packages • AS7C1024 (5V version)

Contextual Info: 12XKx8 3.3V SRAM ^ Features AS7C31024 Logic Block Diagram ♦ High Performance CMOS: tAA=12-35 ns ♦ Fast OE access: t0 E=3-6 ns ♦ Very low power - 270 m W @ 100 M H z - 18. m W @ 10 M H z standby - 3.6 m W @ 10 M H z standby: L version ♦ Automatic CE1/CE2 power down

AS7C1024

Abstract: AS7C1024-12 AS7C1024-15 AS7C1024-20 AS7C31024 AS7C31024-12 AS7C31024-15 AS7C31024-20
Contextual Info: March 2001 AS7C1024 AS7C31024 5V/3.3V 128Kx8 CMOS SRAM Evolutionary Pinout Features • 2.0V data retention • Easy memory expansion with CE1, CE2, OE inputs • TTL/LVTTL-compatible, three-state I/O • 32-pin JEDEC standard packages • AS7C1024 (5V version)

MPS 0733

Abstract: MPS 0729 mps 0720 rochester mps 90 JH23 ldh 0470 cwi 1011 mps 0820 dfl 210 9S40
Contextual Info: High Performance •■ AS7C3 1024 128KX8 3.3V II AS7C31024L CMOS SRAM @ Low voltage 128KX8 CMOS SRAM C o m m o n I / O Features • • • • Organization: 1 3 1 ,0 7 2 w ords x 8 bits Single 3.3 + 0 .3 V pow er supply 5V tolerant I/O specification H igh speed

Contextual Info: February 2004 AS7C31024B 3.3V 128K X 8 CMOS SRAM Features • Easy memory expansion with CE1, CE2, OE inputs • TTL/LVTTL-compatible, three-state I/O • 32-pin JEDEC standard packages • Industrial and commercial temperatures • Organization: 131,072 words x 8 bits

Contextual Info: AS7C1024 AS7C31024 128Kx8 CMOS SRAM Common I/O family Features • O rganization: 1 3 1 ,0 7 2 w o rd s x 8 bits • H ig h speed - 1 0 / 1 2 / 1 5 / 2 0 ns address access tim e - 3 / 3 / 4 / 5 ns o u tp u t enable access tim e • Low p o w e r c o n su m p tio n available

Contextual Info: Il AS7C1024 AS7C1024L AS7C31024 AS7C31024L 128Kx8 CM OS SRAM Common I/O family Features • O rganization: 13 1 ,0 7 2 w o rd s x 8 bits • H igh speed - 1 0 / 1 2 / 1 5 / 2 0 ns address access tim e - 3 / 3 / 4 / 5 ns o u tp u t enable access tim e • Low p o w e r c o n su m p tio n available

as7c1024a-15jc

Contextual Info: May 2001 Advance Information AS7C1024A AS7C31024A 5V/3.3V 128KX8 CMOS SRAM Evolutionary Pinout Features • Latest 6T 0.25u CMOS technology • Easy memory expansion with CE1, CE2, OE inputs • TTL/LVTTL-compatible, three-state I/O • 32-pin JEDEC standard packages

Contextual Info: May 2001 AS7C1024 AS7C31024 5V/3.3V 128Kx8 CMOS SRAM Evolutionary Pinout Features • Easy memory expansion with CE1, CE2, OE inputs • TTL/LVTTL-compatible, three-state I/O • 32-pin JEDEC standard packages • AS7C1024 (5V version) • AS7C31024 (3.3V version)

Contextual Info: August 2000 AS7C1024 AS7C31024 5V/3.3V 128Kx8 CMOS SRAM Evolutionary Pinout Features • 2.0V data retention • Easy memory expansion with CE1, CE2, OE inputs • TTL/LVTTL-compatible, three-state I/O • 32-pin JEDEC standard packages • AS7C1024 (5V version)

AS7C1024

Abstract: AS7C1024-10 AS7C1024-12 AS7C1024-15 AS7C1024-20 AS7C31024 AS7C31024-10 AS7C31024-12 AS7C31024-15 AS7C31024-12TJI
Contextual Info: 2&72% 5#4<<<# $6:&4357 $6:&64357 8926169#45;.ð;#&026#65$0#+(YROXWLRQDU\#3LQRXW, HDWXUHV • AS7C1024 (5V version) • AS7C31024 (3.3V version) • Industrial and commercial temperatures • Organization: 131,072 words x 8 bits • High speed - 10/12/15/20 ns address access time

Contextual Info: High Performance 128Kx8 3.3 V CMOS SRAM H AS7C31024 AS7C31024L PRELIMINARY Low Voltage 128Kx8 CMOS SRAM Common I/O FEATU RES Equal access and cycle times • Organization: 131,072 words x 8 bits • Easy memory expansion with CE1, CE2 and OE inputs • Single 3.3 ±0.3V power supply

AS7C1024

Abstract: AS7C31024
Contextual Info: September 2001 AS7C1024 AS7C31024 5V/3.3V 128Kx8 CMOS SRAM Evolutionary Pinout Features • Easy memory expansion with CE1, CE2, OE inputs • TTL/LVTTL-compatible, three-state I/O • 32-pin JEDEC standard packages • AS7C1024 (5V version) • AS7C31024 (3.3V version)

C31024

Contextual Info: Preliminary information •■ AS7C31024LL A 3.3V 12 8 K X 8 Intelliwatt low power CM OS SRAM Features • • • • Intelliwatt active power reduction circuitry 2.7V to 3.6Yoperating range Organization: 131,072 words x 8 bits High speed - 55/ 7 0 /1 0 0 ns address access time

alks

Abstract: as7c1024a-15jc
Contextual Info: March 2001 Advance Information AS7C1024A AS7C31024A 5V/3.3V 128KX8 CMOS SRAM Evolutionary Pinout Features • Latest 6T 0.25u CMOS technology • 2.0V data retention • Easy memory expansion with CE1, CE2, OE inputs • TTL/LVTTL-compatible, three-state I/O

as7c1024a-15jc

Contextual Info: September 2001 Advance Information AS7C1024A AS7C31024A 5V/3.3V 128KX8 CMOS SRAM Evolutionary Pinout Features • Latest 6T 0.25u CMOS technology • Easy memory expansion with CE1, CE2, OE inputs • TTL/LVTTL-compatible, three-state I/O • 32-pin JEDEC standard packages

DRAM 256 X 1, 18 PDIP

Abstract: 64K X 4 SRAM mmui
Contextual Info: A Contents Fast SRAM Low Voltage Fast SRAM Short Form 1995 AS7C164 8K x 8 3 AS7C256 32K x 8 4 AS7C259 32K x 9 5 AS7C512 64K x 8 6 AS7C1024 128K x 8 300/400 mil 7 AS7C1028 256K x 4 400 mil 8 AS7C3256 32K x 8 3.3V 9 AS7C3512 64K x 8 3.3V 10 AS7C31024 128K x 8

310241

Abstract: A83Z
Contextual Info: High Performance •■ AS7C3 1024 128KX8 3.3V II AS7C31024L CMOS SRAM @ Low voltage 128KX8 CMOS SRAM C o m m o n I / O Features • O r g a n iz a tio n : 1 3 1 ,0 7 2 w o r d s x 8 b its • E q u a l a c c e ss a n d c y c le tim e s • S in g le 3 .3 + 0 .3 V p o w e r s u p p ly

AS7C1024A

Abstract: AS7C31024A as7c1024a-15jc
Contextual Info: February 2002 Advance Information AS7C1024A AS7C31024A 5V/3.3V 128KX8 CMOS SRAM Evolutionary Pinout Features • Latest 6T 0.25u CMOS technology • Easy memory expansion with CE1, CE2, OE inputs • TTL/LVTTL-compatible, three-state I/O • 32-pin JEDEC standard packages

Contextual Info: April 2000 AS7C1024 AS7C31024 5V/3.3V 128Kx8 CMOS SRAM Evolutionary Pinout Features • 2.0V data retention • Easy memory expansion with CE1, CE2, OE inputs • TTL/LVTTL-compatible, three-state I/O • 32-pin JEDEC standard packages • AS7C1024 (5V version)