AS4C4M32S Search Results

AS4C4M32S-6BIN

Abstract: AS4C4M32S
Contextual Info: AS4C4M32S Revision History AS4C4M32S- 90 Ball TFBGA PACKAGE Revision Rev 1.0 Rev 2.0 Rev 3.0 Details Preliminary datasheet Added 166MHz option -6 clock cycle time Typing error page 1 – change to header of Key Specificatons from AS4C8M32S to AS4C4M32S Typing error Frequency in Ordering information

AS4C4M32

Contextual Info: AS4C4M32S 4M x 32 bit Synchronous DRAM SDRAM Alliance Memory Confidential Features • • • • • • • • • • • Clock rate: 166 MHz Fully synchronous operation Internal pipelined architecture 1M word x 32-bit x 4-bank Programmable Mode - CAS Latency: 2, or 3

Contextual Info: AS4C4M32S 4M x 32 bit Synchronous DRAM SDRAM Alliance Memory Confidential Features • • • • • • • • • • • Clock rate: 166 MHz Fully synchronous operation Internal pipelined architecture 1M word x 32-bit x 4-bank Programmable Mode - CAS Latency: 2, or 3

Contextual Info: AS4C4M32S 4M x 32 bit Synchronous DRAM SDRAM Confidential Advanced (Rev. 2.0, Feb. /2013) Features •              Overview The 128Mb AS4C4M32S SDRAM is a highspeed CMOS synchronous DRAM containing 128 Mbits. It is internally configured as a quad 1M x 32

AS4C4M32S-7TCN

Abstract: AS4C4M32S
Contextual Info: AS4C4M32S 4M x 32 bit Synchronous DRAM SDRAM (Rev.3.0, May. /2014) Alliance Memory Confidential Features • • • • • • • • • • • Clock rate: 143/166 MHz Fully synchronous operation Internal pipelined architecture 1M word x 32-bit x 4-bank