80960KX Search Results

D8905

Abstract: "printer controller"
Contextual Info: PRINTERS DESTINY TECHNOLOGY CORPORATION D8905 Page Printer Coprocessor • ■ ■ ■ ■ ■ ■ ■ ■ ■ Optimized For Intel i960 Processor Family 40960Sx, 80960Kx, 80960Cx Programmable Wait States For Various Memory and I/O Devices Supports Interleave Memory

80960JD

Abstract: C6000 SPRU190 TMS320C6000 TMS320C6202 TMS320C6203C
Contextual Info: Application Report SPRA538B - August 2001 TMS320C6000 Expansion Bus to 80960Kx/Jx Microprocessor Interface Zoran Nikolic DSP Applications ABSTRACT This application report describes how to interface the Texas Instruments TI TMS320C6000 (C6000) digital signal processor (DSP) to the Intel 80960Kx/Jx

transistor 778

Abstract: cpu 80960kx printer controller 80960SX Destiny d5001 D8905
Contextual Info: PRINTERS DESTINY TECHNOLOGY CORPORATION D5001 Page Printer Coprocessor • ■ ■ ■ ■ ■ ■ ■ ■ ■ Optimized For Intel i960 Processor Family 80960Sx, 80960Kx, 80960Jx and 80960Cx Supports Up to 1200 dpi Resolutions Band Processing Requires Less

Contextual Info: in te i. 1.0 82961KA W Û T [P^EWOH operate in the non-impact printer environment; how­ ever, many of its features make it extremely wellsuited for other applications. The 82961 KA provides a direct interface between the Intel 80960Kx micro­ processor and system memory, communication

SPRU190

Abstract: TMS320C6000 80960JD C6000 TMS320C6202 TMS320C6000 SPRU190
Contextual Info: Application Report SPRA538B - August 2001 TMS320C6000 Expansion Bus to 80960Kx/Jx Microprocessor Interface Zoran Nikolic DSP Applications ABSTRACT This application report describes how to interface the Texas Instruments TI TMS320C6000 (C6000) digital signal processor (DSP) to the Intel 80960Kx/Jx

Contextual Info: 80960JS/JC 3.3 V Microprocessor Advance Information Datasheet Product Features • Pin/Code Compatible with all 80960Jx Processors ■ High-Performance Embedded Architecture — One Instruction/Clock Execution — Core Clock Rate is: 80960JS lx the Bus Clock

Contextual Info: intJ. 2-MBIT 128K x 16, 256K x 8 LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY 28F200BL-T/B, 28F002BL-T/B m Low Voltage Operation for Very Low Power Portable Applications — Vcc = 3.0V-3.6 V • Automatic Power Savings Feature — 0.8 mA Typical Ice Active Current in

Contextual Info: in tj 2-MBIT 128K x 16, 256K x 8 BOOT BLOCK FLASH MEMORY FAMILY 28F200BX-T/B, 28F002BX-T/B • x8/x16 Input/Output Architecture — 28F200BX-T, 28F200BX-B — For High Performance and High Integration 16-bit and 32-bit CPUs ■ x8-only Input/Output Architecture

Contextual Info: 80960RP 1.0 1.2 ABOUT THIS DOCUMENT Terminology In this document, the following terms are used: This data sheet contains ADVANCE INFORMATION about Intel’s i960 RP processor, including a func­ tional overview, mechanical data package signal locations and simulated thermal characteristics ,

Contextual Info: in te i 1-MBIT 128K X 8 BOOT BLOCK FLASH MEMORY 2 8 F 0 0 1 B X -T /2 8 F 0 0 1 B X -B /2 8 F 0 0 1 B N -T /2 8 F 0 0 1 B N -B • High-Integration Blocked Architecture — One 8 KB Boot Block w/Lock Out — Two 4 KB Parameter Blocks — One 112 KB Main Block

Contextual Info: in te l A28F400BX-T/B 4-MBIT 256K x16, 512K x8 BOOT BLOCK FLASH MEMORY FAMILY Automotive x8/x16 Input/Output Architecture — A28F400BX-T, A28F400BX-B — For High Performance and High Integration 16-bit and 32-bit CPUs Optimized High Density Blocked Architecture

132-Lead

Abstract: AD30/ako 451 960
Contextual Info: A E W Â N l ! DKIIF ß}[ü iflA 70® ß !0 in te l 80960J A /JF EMBEDDED 32-BIT MICROPROCESSOR High-Performance Embedded Architecture — One Instruction/Clock Execution — Load/Store Programming Model — Sixteen 32-Bit Global Registers — Sixteen 32-Bit Local Registers

Contextual Info: in tj. 28F400BX-T/B, 28F004BX-T/B 4 MBIT 256K x16, 512K x8 BOOT BLOCK FLASH MEMORY FAMILY • x8/x16 Input/Output Architecture — 28F400BX-T, 28F400BX-B — For High Performance and High Integration 16-bit and 32-bit CPUs ■ Very High-Performance Read

Contextual Info: P fö H y K ä M Ä G W in te i 80L960JA/JF 3.3V EMBEDDED 32-BIT MICROPROCESSOR 3.3 V Version o f the 80960JA/JF Processor Pin/Code Compatible with all 80960Jx Processors High-Performance Embedded Architecture — One Instruction/Clock Execution — Load/Store Programming Model

28F001

Abstract: intel 28F001BXT
Contextual Info: in t e i, 28F001BX-T/28F001BX-B 1M 128K x 8 CMOS FLASH MEMORY • High Integration Blocked Architecture — One 8KB Boot Block w/Lock Out — Two 4KB Parameter Blocks — One 112KB Main Block ■ 10,000 Erase/Program Cycles Minimum Per Block ■ Simplified Program and Erase

micro instruction set of I960 hx

Abstract: 80960CA 80960CF 80960HA 80960HD 80960HT 80960JA Intel i960
Contextual Info: Intel i960® Processors i960® Architecture Family Product Highlights • 32-bit register-based RISC core in all processors ■ Code compatibility across entire product line ■ Broad selection of price and performance levels ■ Ideal for networking and imaging

3165* intel

Abstract: 82360SL intel 80386SL twc np 6001 28f200 tsop intel 28f200bx 28F002BX 28F002BX-B 28F002BX-T 28F200BX
Contextual Info: INTEL CORP HEHORY/PLD/ SbE D • 4fl2bl?b 007bBS3 flTb m i T L Z 0M lF K ß ! ilÄ T 0®If!!] in te l 'T W o 'K V ¿ k 28F200BX-T/B, 28F002BX-T/B 2 MBIT (128K x 16, 256K x 8 BOOT BLOCK FLASH MEMORY FAMILY x8/x16 Input/Output Architecture — 28F200BX-T, 28F200BX-B

intel CORE i3 instruction set

Abstract: intel packaging handbook 240800
Contextual Info: 80960JA/JF/JD/JT 3.3 V Embedded 32Bit Microprocessor Preliminary Datasheet Product Features • Pin/Code Compatible with all 80960Jx Processors ■ High-Performance Embedded Architecture — One Instruction/Clock Execution — Core Clock Rate is: 80960JA/JF lx the Bus Clock

i960RP

Contextual Info: i960 1.0 ABOUT THIS DOCUMENT 1.2 This data sheet contains advance inform ation about Intel’s i960 RP I/O processor at 5 Volts referred to as 80960R P 33/5.0 , including a fu n ctio n a l overview, m echanical data (package signal locations and simulated therm al characteristics), targeted electrical

Contextual Info: ß R IH L D ß ilD IM D O T r in te i 80960JD EMBEDDED 32-BIT MICROPROCESSOR Pin/Code Compatible with all 80960Jx Processors High-Performance Embedded Architecture — One Instruction/Clock Execution — Core Clock Rate is 2x the Bus Clock — Load/Store Programming Model

Contextual Info: PRELIMINARY 80960J A/JF EMBEDDED 32-BIT MICROPROCESSOR • Pin/Code Compatible with all 80960Jx Processors ■ ■ High Bandwidth Burst Bus — 32-Bit Multiplexed Address/Data — Programmable Memory Configuration — Selectable 8-, 16-, 32-Bit Bus Widths

Contextual Info: 2-MBIT 128K x 16, 256K x 8 LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY 28F200BL-T/B , 28F 002B L-T/B • SRAM-Compatible Write Interface ■ Low Voltage Operation for Very Low Power Portable Applications — VCc - 3.0V-3.6V ■ Automatic Power Savings Feature

k 4431

Contextual Info: in te i 28F200BX-T/B, 28F002BX-T/B 2 MBIT 128K x 16,256K x 8 BOOT BLOCK FLASH MEMORY FAMILY x6/x16 Input/Output Architecture — 28F200BX-T, 28F200BX-B — For High Performance and High Integration 16-bit and 32-bit CPUs Very High-Performance Read — 60/80 ns Maximum Access Time

80960JA

Abstract: 80960JD 80960JF A80960JD NG80960JD 132-lead 27248 intel packaging handbook 240800
Contextual Info: A PRELIMINARY 80960JD EMBEDDED 32-BIT MICROPROCESSOR • Pin/Code Compatible with all 80960Jx Processors ■ High-Performance Embedded Architecture — One Instruction/Clock Execution — Core Clock Rate is 2x the Bus Clock — Load/Store Programming Model