7C335 Search Results

7C335

Abstract: C3355 CY7C335 7c332 83HM
Contextual Info: 7c335: 7/16/91 Revision: Thursday, January 13, 1994 7C335 Universal Synchronous EPLD Features D 100ĆMHz output registered operation D Twelve I/O macrocells, each having: Ċ Registered, threeĆstate I/O pins Ċ Input and output register clock seĆ lect multiplexer

256K x 8 SRAM CY7C128A SRAM

Abstract: 5962-86705 PLD28 5962-89935 pld20ra10 5962-89598 CY7C132 cy7c291 PLD20RA PLDC20G10
Contextual Info: Military Product Selector Guide Static RAMs Size Organization Pins DIP SMD Number Part Number Speed (ns) ICC/ISB/ICCDR (mA @ ns) 883 Availability 1K 256 x 4 22 CY7C122 5962-88594 tAA = 25, 35 90 @ 25 Now 4K 1K x 4—Separate I/O 24S CY7C150 5962-88588 tAA = 25

transistor c331

Abstract: c331 transistor C3318 C3317 C331 C3311 C331 datasheet CY7C331 20HC c331 equivalent
Contextual Info: CY7C331 Asynchronous Registered EPLD Features • Low power — 90 mA typical ICC quiescent • Twelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — 180 mA ICC maximum — UV-erasable and reprogrammable — One feedback flip-flop with input coming from the

TCO - 909 F 10 MHz

Abstract: TCO - 909 C335 CY7C335 TCO - 909 F C335A
Contextual Info: 7C335 CYPRESS Features • 100-MHz output registered operation • Twelve I/O macrocells, each having: — Registered, three-state I/O pins — Input and output register clock se­ lect multiplexer — Feed back multiplexer — Output enable OE multiplexer

7C245

Abstract: b1225 CERAMIC QUAD FLATPACK CQFP 22V10 PAL CMOS device 228X 16R8 7B991 PAL20 7C404 7C128
Contextual Info: Ordering Information RAM, PROM, Dual-Port Static RAM, FIFO, Data Communications PREFIX DEVICE CY CY CY CY CY CY 7C128 62256 7C245 7C006 7C404 7B991 C = CMOS B = BiCMOS SUFFIX -45 D L-70 S L-35 P V-15 J -25 D -5 J MB C C C MB C FAMILY CMOS SRAM - FAST CMOS SRAM - SLOW

c22v10

Abstract: C331M cypress FLASH370 device PAL22V10C-10JC pack1076 16L8 16R4 16R6 CY7C371 c20g
Contextual Info: Simulation of Cypress CPLDs with Mentor's QuickSim II Simulation of Cypress CPLDs and smaller proĆ grammable logic devices in the Mentor Graphics environment is possible without the need for purĆ chasing third party simulation models. Designs ranging the entire density span of Cypress programĆ

CERAMIC QUAD FLATPACK CQFP

Abstract: 64 CERAMIC LEADLESS CHIP CARRIER LCC CERAMIC LEADLESS CHIP CARRIER PACKAGE CERAMIC LEADLESS CHIP CARRIER LCC CY74FCT CERAMIC LEADLESS CHIP CARRIER LCC 24 ic 62256 dual flatpack 8 PAL20 22V10 PAL CMOS device
Contextual Info: Ordering Information RAM, PROM, Dual-Port Static RAM, FIFO, Data Communications PREFIX DEVICE CY CY CY CY CY CY 7C128 62256 7C245 7C006 7C404 7B991 C = CMOS B = BiCMOS SUFFIX -45 D L-70 S L-35 P V-15 J -25 D -5 J MB C C C MB C FAMILY CMOS SRAM - FAST CMOS SRAM - SLOW

C3357

Abstract: c3358 CERAMIC LEADLESS CHIP CARRIER diode c335 c3356 c3355 C335 CY7C335-66PC CY7C335 C3354
Contextual Info: fax id: 6018 1CY 7C33 5 7C335 Universal Synchronous EPLD Features — 2-ns input set-up and 9-ns output register clock to output • 100-MHz output registered operation • Twelve I/O macrocells, each having: — Registered, three-state I/O pins — 10-ns input register clock to state register clock

TCO - 909 F 10 MHz

Abstract: TCO - 909 F CERAMIC LEADLESS CHIP CARRIER C335 CY7C335
Contextual Info: 7C335 CYPRESS Features • 100-MHz output registered operation • Twelve I/O macrocells, each having: — Registered, three-state I/O pins — Input and output register clock se­ lect multiplexer — Feed back multiplexer — Output enable OE multiplexer

qml-38535

Abstract: GDIP4-T28
Contextual Info: _ LÏA R E V I S I O N S _ _ _ I DESCRIPTION |D A T E YR-MO-DA | APPROVED REV SHEET REV 15 SHEET REV OF 16 17 18 STATUS 19 20 REV SHEETS 1 SHEET PMIC 2 3 4 5 7 DEPENSE KENNETH RICE STANDARDIZED MILITARY

Contextual Info: _ 7C335 Universal Synchronous EPLD SEMICONDUCTOR Features • 100-MHz output registered operation • Twelve I/O macrocells, each having: — Registered, three-state I/O pins — Input and output register clock se­ lect multiplexer

cy7c9101

Abstract: CY2901 CY7C190 PLD20RA10 CY2149 CY7C122 CY7C148 CY7C149 CY7C150 22V10-Macrocell
Contextual Info: Military Product Selector Guide Static RAMs Size Organization 64 64 1K 1K 4K 4K 4K 4K 4K 8K 8K 16K 16K 16K 16K 16K 16K 16K 16K 16K 32K 32K 32K 32K 32K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 256K 256K 256K 256K 256K 256K 256K 1M 1M

PLD28

Abstract: 22V10-Macrocell 5962-86705 5962-89598 cy7c291 PLDC20G10 CY6116A CY7C128A CY7C168A CY7C185A
Contextual Info: Military Product Selector Guide Static RAMs Size Organization Pins DIP SMD Number Part Number Speed (ns) ICC/ISB/ICCDR (mA @ ns) Availability 16K 2K x 8—CS Power-Down 24S CY7C128A 5962-89690 tAA = 20, 25 125 @ 20 Now 16K 2K x 8—CS Power-Down 24S CY7C128A

c677

Contextual Info: I U J O J . / / 1 0 /9 1 Revision: Friday, March 2 6 ,1993b M fP ? 1993 7C335 7J s CYPRESS SEMICONDUCTOR Universal Synchronous EPLD construct very high performance state ma­ chines. The architecture of the 7C335, consist­ ing of the user-configurable output macrocell, bidirectional I/O capability, input reg­

Contextual Info: fax id: 6018 7C335 3F CYPRESS Universal Synchronous EPLD Features — 2-ns in p u t se t-u p and 9-ns o u tp u t re g is te r c lo c k to o u tp u t • 100-MHz o u tp u t re g iste re d o p e ra tio n • Tw elve I/O m a c ro c e lls , each h a vin g :

b1225

Abstract: application PAL 16v8 Neuron Chip 3150 7c63000a 16V8 BGA and eQFP Package 62256L EEPROM 25xxx 25xxx 48-pin TSOP
Contextual Info: Ordering Information PHYSICAL LAYER DEVICES PREFIX CY CY CY CY SUFFIX DEVICE P 15G P 15G P 25G S 25G 04 04 01 01 01 DX 02 DX 01 DX K100 – BG – BG – AT – MG C T C T C T C FAMILY QUAD HOTLINK II TRANSCEIVER QUAD HOTLINK II SERDES OC-48 SERDES PROCESSING

Contextual Info: February 2003 7C33512NTD16A 7C33512NTD18A 3.3V 512K x 16/18 65$0 ZLWK 17'TM Features • • • • • • • • • • • • • • • • • Organization: 524,288 words × 16 or 18 bits NTD 1 architecture for efficient bus operation Fast clock speeds to 166 MHz in LVTTL/LVCMOS

61S11

Contextual Info: fax id: 6016 CY7C331 CYPRESS Asynchronous Registered EPLD Features • Twelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coming from the I/O pin — Independent product term set, reset, and clock in­

Contextual Info: 7C335 PRELIMINARY CYPRESS SEMICONDUCTOR Features • 83-MHz registered pipelined operation • Ttoelve I/O macrocells, each having: — Registered, three-state I/O pins — Input and output register clock se­ lect multiplexer — Feed back multiplexer — Output enable OE multiplexer

CY6116A

Abstract: CY7C128A CY7C168A CY7C185A CY7C198 CY7C199 CY37128 5962-85525 84036 Product Selector Guide
Contextual Info: Military Product Selector Guide Static RAMs Size Organization Pins DIP Part Number SMD Number Speed (ns) ICC/ISB/ICCDR (mA @ ns) Availability 16K 2K x 8—CS Power-Down 24S CY7C128A 5962-89690 tAA = 20, 25 125 @ 20 Now 16K 2K x 8—CS Power-Down 24S CY7C128A

16v8 PLD

Abstract: 48C101 7c63000a 7C128 2061A B1225 CERAMIC QUAD FLATPACK CQFP
Contextual Info: Ordering Information RAM, PROM, Dual-Port Static RAM, FIFO, Data Communications PREFIX DEVICE CY CY CY CY CY CY 7C128 62256L 7C245L 7C09389V 7C4292V 7B991 C = CMOS B = BiCMOS SUFFIX -45 D M B -70 S C -35 P C -15 J C -25 AS C -5 J C FAMILY CMOS SRAM - FAST

application PAL 16v8

Abstract: 7c63000a CERAMIC LEADLESS CHIP CARRIER LCC 24 62256L K100 BGA and eQFP Package Neuron Chip 3150 CYPRESS B1225 PLD 22V10
Contextual Info: Ordering Information PHYSICAL LAYER DEVICES PREFIX CY CY CY CY SUFFIX DEVICE P 15G P 15G P 25G S 25G 04 04 01 01 01 DX 02 DX 01 DX K100 - BG - BG - AT - MG C T C T C T C FAMILY QUAD HOTLINK II TRANSCEIVER QUAD HOTLINK II SERDES OC-48 SERDES PROCESSING T = SURFACE-MOUNTED DEVICES TO BE TAPE AND REELED

TCO - 909

Abstract: TCO - 909 F 10 MHz CERAMIC LEADLESS CHIP CARRIER CY7C335 CY7C335-50
Contextual Info: fax id: 6018 7C335 Universal Synchronous EPLD Features — 2-ns input set-up and 9-ns output register clock to output 100-MHz output registered operation Twelve I/O macrocells, each having: — 10-ns input register clock to state register clock — Registered, three-state I/O pins

transistor c331

Abstract: c331 transistor c331 c331 equivalent C3318 C3319 C3314 c3317 C3311 transistor c331 datasheet
Contextual Info: fax id: 6016 1CY7C331 CY7C331 Asynchronous Registered EPLD Features • Low power — 90 mA typical ICC quiescent • Twelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — 180 mA ICC maximum — UV-erasable and reprogrammable