20HC Search Results

68HC05

Abstract: MC68HC705KJ1 MC68HC705KJ1C MC68HC705KJ1CDW MC68HC705KJ1CS MC68HLC705KJ1 MC68HRC705KJ1 HC05CPU Nippon capacitors
Contextual Info: MC68HC705KJ1/D Rev. 1.0 HC 5 MC68HC705KJ1 MC68HLC705KJ1 MC68HRC705KJ1 HCMOS Microcontroller Unit TECHNICAL DATA List of Sections Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

MC68HC705J1A

Abstract: 68HC05 M68HC05 MC68HC705J1AP MC68HRC705J1A MC68HSC705J1A MC68HSR705J1A Nippon capacitors
Contextual Info: MC68HC705J1A/D Rev. 2.0 HC 5 MC68HC705J1A MC68HRC705J1A MC68HSC705J1A MC68HSR705J1A HCMOS Microcontroller Units TECHNICAL DATA List of Sections Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . 5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

74151

Abstract: 74151 pin connection C3406 74151 PIN DIAGRAM 74151 waveform counter schematic diagram 74161 programmer EPLD 22v10 5192JM 74151 multiplexer
Contextual Info: 1CY 7C34 0 fax id: 6100 EPL D Family CY7C340 EPLD Family Multiple Array Matrix High-Density EPLDS Features tion of innovative architecture and state-of-the-art process, the MAX EPLDs offer LSI density without sacrificing speed. • Erasable, user-configurable CMOS EPLDs capable of

31-oq

Abstract: 7C342-25 CY7C342-35HMB 7C342-35 CY7C342 CY7C342B OQ11
Contextual Info: CY7C342 CY7C342B rif CYPRESS 128-Macrocell M AX EPLD Features Functional Description • 128 macrocells in 8 LABs • 8 dedicated inputs, 52 bidirectional I/O pins • Programmable interconnect array • 0.8-micron double-metal CMOS EPROM technology CY7C342

84-PIN

Abstract: CY7C341B
Contextual Info: CY7C341B y CYPRESS Features • 192 macrocells in 12 LABs • 8 dedicated inputs, 64 bidirectional I/O pin • Advanced 0.65-micron CMOS technology to increase performance • Programmable interconnect array • 384 expander product terms • Available in 84-pin HLCC, PLCC, and

L496D

Abstract: 9l reset CY7C331 ST L11922 0423-J
Contextual Info: CY7C331 -W C Y P R E S S Asynchronous Registered EPLD Features • TWelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coining from the I/O pin — Independent product term set,

K12J

Abstract: 100-PIN CY7C346 CY7C346B f 7400
Contextual Info: CY7C346 CY7C346B 5T CYPRESS 128-Macrocell MAX EPLDs Features Functional Description • 128 macrocells in 8 LABs • 20 dedicated inputs, up to 64 bidirec­ tional I/O pins • Programmable interconnect array • 0.8-micron double-metal CMOS EPROM technology CY7C346

C3402

Abstract: 74151 5128LC-1 74151 PIN DIAGRAM 5128LC-2 74151 8 to 1 74151 pin connection function of 74151 22V10-10C CY7C340
Contextual Info: EPLD CY7C340 EPLD Family Multiple Array Matrix High-Density EPLDs Features • Erasable, user-configurable CMOS EPLDs capable of implementing high-density custom logic functions • 0.8-micron double-metal CMOS EPROM technology CY7C34X • Advanced 0.65-micron CMOS technology to increase

2T931A

Abstract: KT853 2T926A KT838A 2T803A 2T809A 2T904A 2T808A 2T603 2T921A
Contextual Info: g V ì^ fg : W SflÉptÉ! W ^ i$ î0 i0 û * W I I m ^7ù£-à.S& m p ,-À-& s i: r& mSÊmÈÈ •ï ' ^ f§ W % a s Ü lg S I W M 7 \ w Jkw s i 4; h# » ik « W 'ï illl ¡ P * te ili -X\ S I Iw 11 4-S U E S T am Ir ¿ « 1 1 1 » , ü i a Î3 & & C nPA BO H H M K

74HCT4046AP

Abstract: OS88 26HC cd74hct4046
Contextual Info: Technical Data F ile N u m b e r CD54/74HC 4046A CD54/74HCT 4046A 1854 Advance Inform ation/ Preliminary Data HA RR IS SE MI C O N D S E CT OR 27E D 43 0 5 2 7 1 ODIT'IOO S I - 5 0 -p 'V D High-Speed CMOS Logic PCI0 UT P C 3 0U T P C 2 0U T PCPQUT 9 2 C S -4 0 5 9 2

transistor c331

Abstract: c331 transistor C3318 C3317 C331 C3311 C331 datasheet CY7C331 20HC c331 equivalent
Contextual Info: CY7C331 Asynchronous Registered EPLD Features • Low power — 90 mA typical ICC quiescent • Twelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — 180 mA ICC maximum — UV-erasable and reprogrammable — One feedback flip-flop with input coming from the

Contextual Info: VARISTOR SPECIFICATION SHEET Date: 2/19/2008 MAIDA STYLE NUMBER D65ZOV151HC DIAMOND SERIES CONTACT Electrical Specifications Physical Specifications Continuous AC Voltage 150 VAC Lead Style 110B1 Continuous DC Voltage 200 VDC Z Nominal 0.3 in. Maximum DC Leakage @ Rated VDC

Contextual Info: VARISTOR SPECIFICATION SHEET Date: 5/13/2005 MAIDA STYLE NUMBER D65ZOV151HC DIAMOND SERIES CONTACT Electrical Specifications Physical Specifications Continuous AC Voltage 150 VAC Lead Style 110B1 Continuous DC Voltage 200 VDC Z Nominal 0.3 in. Maximum DC Leakage @ Rated VDC

Contextual Info: VARISTOR SPECIFICATION SHEET Date: 6/16/2005 MAIDA STYLE NUMBER D65ZOV131HC DIAMOND SERIES CONTACT Electrical Specifications Physical Specifications Continuous AC Voltage 130 VAC Lead Style 110B1 Continuous DC Voltage 175 VDC Z Nominal 0.3 in. Maximum DC Leakage @ Rated VDC

Contextual Info: VARISTOR SPECIFICATION SHEET Date: 4/5/2004 MAIDA STYLE NUMBER D65ZOV131HC DIAMOND SERIES CONTACT Electrical Specifications Physical Specifications Continuous AC Voltage 130 VAC Lead Style 110B1 Continuous DC Voltage 175 VDC Z Nominal 0.3 in. Maximum DC Leakage @ Rated VDC

74HC

Abstract: 7C344 CY7C344 CY7C344B LTAC01
Contextual Info: CY7C344 CY7C344B i f CYPRESS 32-Macrocell MAX EPLD Features Functional Description • High-performance, high-density re­ placement for TTL, 74HC, and cus­ tom logic • 32 macrocells, 64 expander product terms in one LAB • 8 dedicated inputs, 16 I/O pins

C3424

Abstract: 68-PIN 7C342-30 7C342-35 CY7C342 CY7C342B C3422 CY7C342-30HC CY7C342B-30RMB 30RM
Contextual Info: CY7C342 CY7C342B CYPRESS 128-Macrocell MAX EPLD Features Functional Description • 128 macrocells in 8 LABs • 8 dedicated inputs, 52 bidirectional I/O pins • Programmable interconnect array • 0.8-micron double-metal CMOS EPROM technology CY7C342

PM555

Abstract: cd74hct4046 4046A 74HCT4046A
Contextual Info: Technical Data F ile N u m b e r CD54/74HC 4046A CD54/74HCT 4046A 1854 Advance Inform ation/ Preliminary Data High-Speed CMOS Logic Phase-Locked-Loop with VCO C O M P N- m O p e ra tin g p o w e r s u p p ly vo lta g e ra ng e : Features: • O p e ra tin g fre q u e n c y ra n g e o f u p to

MC68HC705J1A

Contextual Info: MC68HC705J1 A/D Rev. 2.0 MC68HC705J1A MC68HRC705J1A MC68HSC705J1A MC68HSR705J1A HCMOS Microcontroller Units TECHNICAL DATA Ä b3b?E4ö 0 1S ÔDL7 3^5 • M O TO R O LA ( S ) IN T E N T IO N A L L Y b3b?24fl DISfiObfi 221 B L A N K List of Sections List of Sections. 3

6 pin 2D 1002 ring COUNTER

Abstract: EGH15CA MGN12 HGR15 ISO 8015 tolerance HGR-30 970004A1 EGR15 HGR25 qh25c
Contextual Info: Linear Guideway Technical Information www.hiwin.com.tw Linear Guideways Technical Information Index Preface .1

TAC01

Contextual Info: CY7C343 CYPRESS SEMICONDUCTOR 64-Macrocell MAX EPLD F eatures F unctional D escription • 64 MAX macrocells in 4 LABs The CY7C343 is a high-performance, high-density erasable programmable logic device, available in 44-pin PLCC and HLCC packages. The CY7C343 contains 64 highly flexible

Contextual Info: ^JCMEMFCONJ NIPPON m in ia t u r e a l u m in u m e l e c t r o l y t ic c a p a c it o r s •Downsized from current standard SME series •Endurance : 85°C 2000 hours •Solvent-proof type, except 350 to 450Vdc, see page 16 f d°wnsi2ed SME ♦SPECIFICATIONS

coating 225

Contextual Info: VARISTOR SPECIFICATION SHEET Date: 5/13/2005 MAIDA STYLE NUMBER D65ZOV131HC DIAMOND SERIES CONTACT Electrical Specifications Physical Specifications Continuous AC Voltage 130 VAC Lead Style 110B1 Continuous DC Voltage 175 VDC Z Nominal 0.3 in. Maximum DC Leakage @ Rated VDC

M68HC05

Abstract: MC68HC05P9A MC68HC05P9ACDW MC68HC05P9ACP MC68HC05P9ADW MC68HC05P9AMDW MC68HC05P9AMP MC68HC05P9AP MC68HC05P9AVDW MC68HC05P9AVP
Contextual Info: Freescale Semiconductor, Inc. Freescale Semiconductor, Inc. MC68HC05P9A/D HC 5 MC68HC05P9A HCMOS Microcontroller Unit TECHNICAL DATA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc.