CY7C342 Search Results

31-oq

Abstract: 7C342-25 CY7C342-35HMB 7C342-35 CY7C342 CY7C342B OQ11
Contextual Info: CY7C342 CY7C342B rif CYPRESS 128-Macrocell M AX EPLD Features Functional Description • 128 macrocells in 8 LABs • 8 dedicated inputs, 52 bidirectional I/O pins • Programmable interconnect array • 0.8-micron double-metal CMOS EPROM technology CY7C342

342-35HM

Contextual Info: CY7C342 CYPRESS SEMICONDUCTOR Features 128-Macrocell MAX EPLDs M A X architecture is 100% u ser configur­ able, allowing the devices to accom m o­ d a te a variety o f in d ependent logic func­ tions. • 128 macrocells in 8 LABs • 8 dedicated inputs, 52 bidirectional

C3424

Abstract: 68-PIN 7C342-30 7C342-35 CY7C342 CY7C342B C3422 CY7C342-30HC CY7C342B-30RMB 30RM
Contextual Info: CY7C342 CY7C342B CYPRESS 128-Macrocell MAX EPLD Features Functional Description • 128 macrocells in 8 LABs • 8 dedicated inputs, 52 bidirectional I/O pins • Programmable interconnect array • 0.8-micron double-metal CMOS EPROM technology CY7C342

68-PIN

Abstract: CY7C342B ULTRA37000TM CY7C342B-30JC
Contextual Info: USE ULTRA37000TM FOR ALL NEW DESIGNS CY7C342B 128-Macrocell MAX EPLD Features 100% user-configurable, allowing the device to accommodate a variety of independent logic functions. • 128 macrocells in eight logic array blocks LABs The 128 macrocells in the CY7C342B are divided into eight

7C342C

Contextual Info: CY7C342 CY7C342B CYPRESS 128-Macrocell MAX EPLD Features F unctional D escrip tion • The CY7C342/CY7C342B is an Erasable P rogram m able Logic Device E P L D in which CM O S E P R O M cells are used to configure logic functions w ithin the device. T he M AX architecture is 100% user confi­

68-PIN

Abstract: CY7C342B
Contextual Info: 42B CY7C342B 128-Macrocell MAX EPLD Features The 128 macrocells in the CY7C342B are divided into 8 Logic Array Blocks LABs , 16 per LAB. There are 256 expander product terms, 32 per LAB, to be used and shared by the macrocells within each LAB. • • •

Contextual Info: CY7C342 CY7C342B CYPRESS SEMICONDUCTOR & 128-Macrocell M A X EPLDs Features Functional Description • 128 macrocells in 8 LABs • 8 dedicated inputs, 52 bidirectional I/O pins • Programmable interconnect array • Available in 68-pin HLCC, PLCC, PGA, and Flatpack

CY7C342

Contextual Info: CY7C342 CYPRESS SEMICONDUCTOR 128-Macrocell MAX EPLDs The speed and density of the CY7C342 allows it to be used in a wide range of applications, from replacement of large amounts of 7400-series TTL logic, to complex controllers and multifunction chips. With greater than 25 times the

tag l9 225 400

Abstract: TAG B6 CY7C342B H-81
Contextual Info: 7c342: 11-4-91 Revision: October 19, 1995 CY7C342B 128ĆMacrocell MAXR EPLDs Features D 128 macrocells in 8 LABs D 8 dedicated inputs, 52 bidirectional The CY7C342B is an Erasable ProgramĆ mable Logic Device EPLD in which CMOS EPROM cells are used to configure

CY7C342-35RMB

Abstract: CY7C342-35HC CY7C342-30HC CY7C342 CY7C342-40RC 7C342-30 7C342-35 CY7C342-35JC propagation delay in IC TTL 7400 CY7C342-35RC
Contextual Info: P R E L IM IN A R Y CYPRESS SEMICONDUCTOR 128-M acrocell CY7C342 CY7C345 M AXTM EPL D s Features Functional Description CY7C342 T h e C Y 7C 342 an d CY7C345 are E ras­ able P rogram m able Logic Devices E P L D s in w hich CM O S E P R O M cells are used to configure logic func­

CY7C342

Abstract: CY7C342B
Contextual Info: This is an abbreviated datasheet. Contact a Cypress Representative for complete specifications. For new designs, please refer to the CY7C342B. CY7C342 128-Macrocell MAX EPLDs Features • • • • • 128 macrocells in 8 LABs 8 dedicated inputs, 52 bidirectional I/O pins

Contextual Info: CY7C342B S / CYPRESS Features • 128-Macrocell MAX EPLDs m a b lc L ogic D evice E P L D in w h ich C M O S E P R O M c e lls a re u se d to c o n fig u re logic fu n c tio n s w ith in th e d ev ice. T h e M A X a rc h ite c tu re is 100% u s e r c o n fig u r­

68 pin plcc socket view bottom

Contextual Info: 68-7747-10 or 68-7747-13 ATMEL ATV 5000 AND CYPRESS CY7C342B 68 PIN PLCC TO PGA CHIP ADAPTERS FEATURES: • Correct-A-Chip technology solves problems associated with the use of alternative IC packages due to availability and obsolescence by eliminating the need for new PCBs.

7C342B

Abstract: 68-PIN CY7C342B k941
Contextual Info: 7C342B:11/91 Revision: July 19, 2000 CY7C342B 128-Macrocell MAX EPLD Features The 128 macrocells in the CY7C342B are divided into 8 Logic Array Blocks LABs , 16 per LAB. There are 256 expander product terms, 32 per LAB, to be used and shared by the macrocells within each LAB.

CY7C342

Abstract: of 7400 Series TTL TTL 7400 cmos logic 7400 series
Contextual Info: 42 CY7C342 128-Macrocell MAX EPLD Features • • • • • 128 macrocells in 8 LABs 8 dedicated inputs, 52 bidirectional I/O pins Programmable interconnect array 0.8-micron double-metal CMOS EPROM technology Available in 68-pin HLCC, PLCC, and PGA packages

7C342-25

Abstract: 7C342-30 7C342-35 CY7C342 CY7C342B
Contextual Info: 7c342: October 19, 1995 This is an abbreviated datasheet. Contact a Cypress Representative for complete specifications. For new designs, please refer to the CY7C342B. CY7C342 128ĆMacrocell MAXR EPLDs put bus. All macrocell feedbacks go to the macrocell array, the exĆ

k941

Abstract: 68-PIN CY7C342B ULTRA37000TM
Contextual Info: USE ULTRA37000TM FOR ALL NEW DESIGNS CY7C342B 128-Macrocell MAX EPLD Features 100% user-configurable, allowing the device to accommodate a variety of independent logic functions. • 128 macrocells in eight logic array blocks LABs The 128 macrocells in the CY7C342B are divided into eight

CY7C342B

Abstract: 7C342B-35 68-PIN CY7C342B15HMB CY7C342B-35RMB CY7C342B-35HC
Contextual Info: 1CY 7C34 2B CY7C342B 128-Macrocell MAX EPLDs Features The 128 macrocells in the CY7C342B are divided into 8 Logic Array Blocks LABs , 16 per LAB. There are 256 expander product terms, 32 per LAB, to be used and shared by the macrocells within each LAB.

CY7C342B

Abstract: EME-6300H
Contextual Info: Qualification Report August 1996, QTP# 95514, Version 1.1 CY7C342B 128-Macrocell MAX EPLD MAX is a register trademark of Altera Coporation. PRODUCT DESCRIPTION (for qualification) Information provided in this document is intended for generic qualification and technically describes the Cypress part supplied:

HR210

Contextual Info: CY7C342 CY7C342B CYPRESS 128-Macrocell MAX EPLD Features Functional Description • 128 macrocells in 8 LABs T he CY 7C342/CY7C342B is an E rasable Program m able Logic Device E P L D in which C M O S E P R O M cells are used to configure logic functions w ithin the device.

TTL 7400

Abstract: CY7C342 7400 datasheet ttl gate 7400 series CMOS Logic ICs 7400 series logic ICs 7400 TTL datasheet CY7C342B 7400series ttl cmos logic 7400 series
Contextual Info: This is an abbreviated datasheet. Contact a Cypress Representative for complete specifications. For new designs, please refer to the CY7C342B. 1CY 7C34 2 fax id: 6103 CY7C342 128-Macrocell MAX EPLDs Features • • • • • 128 macrocells in 8 LABs 8 dedicated inputs, 52 bidirectional I/O pins

CY7C342B-25jc

Abstract: 68-PIN CY7C342B K941
Contextual Info: CY7C342B 128-Macrocell MAX EPLD Features The 128 macrocells in the CY7C342B are divided into 8 Logic Array Blocks LABs , 16 per LAB. There are 256 expander product terms, 32 per LAB, to be used and shared by the macrocells within each LAB. • • • •

G013G

Abstract: 05V3 7C342-30 7C342-35 CY7C342 CY7C342B CY7C342-30RMB K941 12J8 CY7C342-35JC
Contextual Info: CY7C342 CY7C342B ^ CYPRESS 128-Macrocell M AX EPLD Features Functional Description • 128 macrocells in 8 LABs • 8 dedicated inputs, 52 bidirectional I/O pins • Programmable interconnect array • 0.8-micron double-metal CMOS EPROM technology CY7C342

CY7C342-35RMB

Abstract: CY7C342-30HC CY7C342 CY7C342B 4s44 CY7C342-30RMB 7C342-30
Contextual Info: fc.SE D CYPRESS SEMICONDUCTOR • SSôTbhE 0D1D4Û0 41Ô * C Y P CY7C342 CY7C342B :s CYPRESS SEMICONDUCTOR 128-Macrocell MAX EPLDs Features Functional Description • 128 macrocells in 8 LABs • 8 dedicated inputs, 52 bidirectional I/O pins • Programmable interconnect array