7C342 Search Results

tag l9 225 400

Abstract: TAG B6 CY7C342B H-81
Contextual Info: 7c342: 11-4-91 Revision: October 19, 1995 7C342B 128ĆMacrocell MAXR EPLDs Features D 128 macrocells in 8 LABs D 8 dedicated inputs, 52 bidirectional The 7C342B is an Erasable ProgramĆ mable Logic Device EPLD in which CMOS EPROM cells are used to configure

7C342B

Abstract: 68-PIN CY7C342B k941
Contextual Info: 7C342B:11/91 Revision: July 19, 2000 7C342B 128-Macrocell MAX EPLD Features The 128 macrocells in the 7C342B are divided into 8 Logic Array Blocks LABs , 16 per LAB. There are 256 expander product terms, 32 per LAB, to be used and shared by the macrocells within each LAB.

7C342-25

Abstract: 7C342-30 7C342-35 CY7C342 CY7C342B
Contextual Info: 7c342: October 19, 1995 This is an abbreviated datasheet. Contact a Cypress Representative for complete specifications. For new designs, please refer to the 7C342B. 7C342 128ĆMacrocell MAXR EPLDs put bus. All macrocell feedbacks go to the macrocell array, the exĆ

HR210

Contextual Info: 7C342 7C342B CYPRESS 128-Macrocell MAX EPLD Features Functional Description • 128 macrocells in 8 LABs T he CY 7C342/7C342B is an E rasable Program m able Logic Device E P L D in which C M O S E P R O M cells are used to configure logic functions w ithin the device.

74151

Abstract: 74151 pin connection C3406 74151 PIN DIAGRAM 74151 waveform counter schematic diagram 74161 programmer EPLD 22v10 5192JM 74151 multiplexer
Contextual Info: 1CY 7C34 0 fax id: 6100 EPL D Family CY7C340 EPLD Family Multiple Array Matrix High-Density EPLDS Features tion of innovative architecture and state-of-the-art process, the MAX EPLDs offer LSI density without sacrificing speed. • Erasable, user-configurable CMOS EPLDs capable of

31-oq

Abstract: 7C342-25 CY7C342-35HMB 7C342-35 CY7C342 CY7C342B OQ11
Contextual Info: 7C342 7C342B rif CYPRESS 128-Macrocell M AX EPLD Features Functional Description • 128 macrocells in 8 LABs • 8 dedicated inputs, 52 bidirectional I/O pins • Programmable interconnect array • 0.8-micron double-metal CMOS EPROM technology 7C342

C3402

Abstract: 74151 5128LC-1 74151 PIN DIAGRAM 5128LC-2 74151 8 to 1 74151 pin connection function of 74151 22V10-10C CY7C340
Contextual Info: EPLD CY7C340 EPLD Family Multiple Array Matrix High-Density EPLDs Features • Erasable, user-configurable CMOS EPLDs capable of implementing high-density custom logic functions • 0.8-micron double-metal CMOS EPROM technology CY7C34X • Advanced 0.65-micron CMOS technology to increase

256K x 8 SRAM CY7C128A SRAM

Abstract: 5962-86705 PLD28 5962-89935 pld20ra10 5962-89598 CY7C132 cy7c291 PLD20RA PLDC20G10
Contextual Info: Military Product Selector Guide Static RAMs Size Organization Pins DIP SMD Number Part Number Speed (ns) ICC/ISB/ICCDR (mA @ ns) 883 Availability 1K 256 x 4 22 CY7C122 5962-88594 tAA = 25, 35 90 @ 25 Now 4K 1K x 4—Separate I/O 24S CY7C150 5962-88588 tAA = 25

ATPA

Abstract: 7130SA100P 24l01 7C263/4-35C 7164S15Y cy9122-25 7133SA35J 7142sa55 7130sa55p cy2149-45c
Contextual Info: Product Line Cross Reference CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS CY2147-35C CY7C147-35C CY7C147-45C CY7C147-35C CY91L22-35C CY7C122-35C CY2147-45C CY2147-35C CY7C148-35C CY7C148-25C+ CY91L22-45C CY93L422AC CY2147-45C CY7C147-45C CY7C148-45C CY7C148-35C

342-35HM

Contextual Info: 7C342 CYPRESS SEMICONDUCTOR Features 128-Macrocell MAX EPLDs M A X architecture is 100% u ser configur­ able, allowing the devices to accom m o­ d a te a variety o f in d ependent logic func­ tions. • 128 macrocells in 8 LABs • 8 dedicated inputs, 52 bidirectional

C3424

Abstract: 68-PIN 7C342-30 7C342-35 CY7C342 CY7C342B C3422 CY7C342-30HC CY7C342B-30RMB 30RM
Contextual Info: 7C342 7C342B CYPRESS 128-Macrocell MAX EPLD Features Functional Description • 128 macrocells in 8 LABs • 8 dedicated inputs, 52 bidirectional I/O pins • Programmable interconnect array • 0.8-micron double-metal CMOS EPROM technology 7C342

81c78

Abstract: 7C291 5962-8515505RX 27PC256-12 PAL164A 8464C 5C6408 72018 39C10B MACH110 cross reference
Contextual Info: Product Line Cross Reference CYPRESS 2147-35C 2147-45C 2147-45C 2147-45M+ 2147-55C 2147-55M 2148-35C 2148-35C 2148-35M 2148-45C 2148-45C 2148-45M 2148-45M+ 2148-55C 2148-55C 2148-55M 2149-35C 2149-35C 2149-35M 2149-45C 2149-45M 2149-45M 2149-55C 2149-55C 2149-55M

68-PIN

Abstract: CY7C342B ULTRA37000TM CY7C342B-30JC
Contextual Info: USE ULTRA37000TM FOR ALL NEW DESIGNS 7C342B 128-Macrocell MAX EPLD Features 100% user-configurable, allowing the device to accommodate a variety of independent logic functions. • 128 macrocells in eight logic array blocks LABs The 128 macrocells in the 7C342B are divided into eight

7C342C

Contextual Info: 7C342 7C342B CYPRESS 128-Macrocell MAX EPLD Features F unctional D escrip tion • The 7C342/7C342B is an Erasable P rogram m able Logic Device E P L D in which CM O S E P R O M cells are used to configure logic functions w ithin the device. T he M AX architecture is 100% user confi­

MSM 6290

Abstract: msm 5562 27c256 intel 62c512 AP 2068 27C512 microchip 62256 57C256 27C512 SGS-THOMSON 27C512-150
Contextual Info: Product Line Cross Reference CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS 2147-35C 7C147-35C 27S03M 54S189M 7C170A-45M 7C170A-35M 2147-45C 2147-35C 27S07AC 7C190-25C 7C171A-35C 7C171A-25C 2147-45C 7C147-45C 27S07AM 7C190-25M 7C171A-45M 7C171A-35M+ 2147-45M+

pin configuration IC 74151

Abstract: IC 74151 diagram and truth table IC TTL 7400 diagram and truth table ic 74151 full adder using Multiplexer IC 74151 Multiplexer IC 74151 programmer manual EPLD cypress IC 7400 SERIES ALL DATA programming manual EPLD cy7c342
Contextual Info: CYPRESS SEMICONDUCTOR HOE D 256*^2 DD05427 5 ICYP 7 T V d -/3 -4 7 CY7C340 EPLD Family « 1 ^ CYPRESS SEMICONDUCTOR Multiple Array Matrix High-Density EPLDs Features General Description • Erasable, user-configurable CMOS EPLDs capable of implementing high-density custom logic functions

68-PIN

Abstract: CY7C342B
Contextual Info: 42B 7C342B 128-Macrocell MAX EPLD Features The 128 macrocells in the 7C342B are divided into 8 Logic Array Blocks LABs , 16 per LAB. There are 256 expander product terms, 32 per LAB, to be used and shared by the macrocells within each LAB. • • •

74151 PIN DIAGRAM

Abstract: 74151 22v10 5192JM CY7C340 PRODUCT CHANGE PALC22V10B programmer EPLD CY7C340 CY7C341B CY7C342B
Contextual Info: 40 EPLD CY7C340 EPLD Family Multiple Array Matrix High-Density EPLDs Features • Erasable, user-configurable CMOS EPLDs capable of implementing high-density custom logic functions • 0.8-micron double-metal CMOS EPROM technology CY7C34X • Advanced 0.65-micron CMOS technology to increase

Contextual Info: 7C342 7C342B CYPRESS SEMICONDUCTOR & 128-Macrocell M A X EPLDs Features Functional Description • 128 macrocells in 8 LABs • 8 dedicated inputs, 52 bidirectional I/O pins • Programmable interconnect array • Available in 68-pin HLCC, PLCC, PGA, and Flatpack

CY7C342

Contextual Info: 7C342 CYPRESS SEMICONDUCTOR 128-Macrocell MAX EPLDs The speed and density of the 7C342 allows it to be used in a wide range of applications, from replacement of large amounts of 7400-series TTL logic, to complex controllers and multifunction chips. With greater than 25 times the

22V10-Macrocell

Abstract: 99522 PLD20RA10 22V10D 5962-89598 cy7c291 CY7C425 PALC22V10B CY6116A CY7C128A
Contextual Info: Military Product Selector Guide Static RAMs Size Organization Pins DIP SMD Number Part Number 16K 2K x 8—CS Power-Down 24S CY7C128A 16K 2K x 8—CS Power-Down 24 CY6116A 64K 8K x 8—CS Power-Down 28S CY7C185A 256K 32K x 8—CS Power-Down 28 CY7C198 256K

cy7c9101

Abstract: CY2901 CY7C190 PLD20RA10 CY2149 CY7C122 CY7C148 CY7C149 CY7C150 22V10-Macrocell
Contextual Info: Military Product Selector Guide Static RAMs Size Organization 64 64 1K 1K 4K 4K 4K 4K 4K 8K 8K 16K 16K 16K 16K 16K 16K 16K 16K 16K 32K 32K 32K 32K 32K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 256K 256K 256K 256K 256K 256K 256K 1M 1M

CY7C342-35RMB

Abstract: CY7C342-35HC CY7C342-30HC CY7C342 CY7C342-40RC 7C342-30 7C342-35 CY7C342-35JC propagation delay in IC TTL 7400 CY7C342-35RC
Contextual Info: P R E L IM IN A R Y CYPRESS SEMICONDUCTOR 128-M acrocell 7C342 CY7C345 M AXTM EPL D s Features Functional Description 7C342 T h e C Y 7C 342 an d CY7C345 are E ras­ able P rogram m able Logic Devices E P L D s in w hich CM O S E P R O M cells are used to configure logic func­

Contextual Info: CY7C340 EPLD Family 0 CYPRESS Multiple Array Matrix High-Density EPLDs — VHDL simulation ViewSim Features • Erasable, user-configurable CMOS EPLDs capable o f implementing highdensity custom logic functions • 0.8-micron double-metal CMOS EPROM technology (CY7C34X)