7C332 Search Results

L496D

Abstract: 9l reset CY7C331 ST L11922 0423-J
Contextual Info: CY7C331 -W C Y P R E S S Asynchronous Registered EPLD Features • TWelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coining from the I/O pin — Independent product term set,

Contextual Info: CY7C330 C Y P R E S S •0 Features • Twelve I/O macrocells each having: — registered, three-state I/O pins — input register clock select multi­ plexer — feed back multiplexer — output enable OE multiplexer • All twelve macrocell state registers

Contextual Info: Asynchronous Registered EPLD 13 inputs, 12 feedback VO pins, plus 6 shared I/O macrocell feedbacks for a total of 31 true and complementary inpnts High speed: 20 ns maximum tpo Security bit Space-saving 28-pin slim-line DIP package; also available in 28-pin

7c331-35

Contextual Info: s :^é= , CY7C331 •jS QYPRESS -■ W SEMICONDUCTOR Asynchronous Registered EPLD Features • TVelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coining from the I/O pin — Independent product term set,

Contextual Info: H ig h P e rf o rm a n c e 32K x32 C M O S SRA M •■ A S7C 33232F II 3 2 K x 3 2 Synchronous bu rst SRAM Prelim inary information • O rganization: 32,768 w ords x 32 bits • Fully synchronous pipelined operation • F low -through o r pipelined • Fast clocking speed: 1 0 0 /7 5 /6 6 MHz

C30B

Contextual Info: H igh p erfo r m a n c e 2 5 6 / 5 1 2 Kbyte 3.3V Cache m o d u le s •■ A S7M C 30 B E 3 2 5 6 A S7M C 30 B (E )351 2 J l C O A S t c o m p a ti b l e 2 5 6 / 5 1 2 Kbyte S R A M cache m o d u le s Preliminary information Features Pin diagram • Fully co m p a tib le w ith COASt 1.4, 3 .0 , 3 .x

Contextual Info: 7C33256PFD16A 7C33256PFD18A December 2002 3.3V 256K x 16/18 pipeline burst synchronous SRAM Features • Organization: 262,144 words × 16 or 18 bits • Fast clock speeds to 166 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.5/4.0/5.0 ns • Fast OE access time: 3.5/4.0/5.0 ns

10PACKAGE

Contextual Info: September 2001 Preliminary Information 7C33256PFD32A 7C33256PFD36A 3.3V 256K x 32/36 pipeline burst synchronous SRAM Features • Organization: 262,144 words x 32 or 36 bits • Fast clock speeds to 166 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.5/3.8/4.0/5.0 ns

TCO - 909 F 10 MHz

Abstract: TCO - 909 C335 CY7C335 TCO - 909 F C335A
Contextual Info: CY7C335 CYPRESS Features • 100-MHz output registered operation • Twelve I/O macrocells, each having: — Registered, three-state I/O pins — Input and output register clock se­ lect multiplexer — Feed back multiplexer — Output enable OE multiplexer

Contextual Info: 7C332 ¡W CYPRESS SEMICONDUCTOR 13 in p u t m acrocells, each having: — C om plem entary input — R egister, latch, o r tra n s p a re n t access — Two clock sources Features • • Registered Combinatorial EPLD 12 I/O m acrocells each having: — R egistered, latched, o r tra n s p a re n t

Contextual Info:  $6& 9.ðV\QFKURQRXVEXUVW65$0 )HDWXUHV • Asynchronous output enable control • ADSP, ADSC, ADV, MODE burst control pins • PentiumTM or PowerPCTM count sequence • Transparent logic support for 1 or 2 CPUs • Single 3.3 ± 0.3V power supply

MSM 6290

Abstract: msm 5562 27c256 intel 62c512 AP 2068 27C512 microchip 62256 57C256 27C512 SGS-THOMSON 27C512-150
Contextual Info: Product Line Cross Reference CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS 2147-35C 7C147-35C 27S03M 54S189M 7C170A-45M 7C170A-35M 2147-45C 2147-35C 27S07AC 7C190-25C 7C171A-35C 7C171A-25C 2147-45C 7C147-45C 27S07AM 7C190-25M 7C171A-45M 7C171A-35M+ 2147-45M+

TCO - 909 F 10 MHz

Abstract: TCO - 909 F CERAMIC LEADLESS CHIP CARRIER C335 CY7C335
Contextual Info: CY7C335 CYPRESS Features • 100-MHz output registered operation • Twelve I/O macrocells, each having: — Registered, three-state I/O pins — Input and output register clock se­ lect multiplexer — Feed back multiplexer — Output enable OE multiplexer

C3317

Abstract: L1190 CY7331
Contextual Info: Asynchronous Registered EPLD Features • TWelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coming from the I/O pin — Independent product term set, reset, and clock inputs on all

Contextual Info: CY7C331 CYPRESS — . = SEMICONDUCTOR Asynchronous Registered EPLD T\velve I/O macrocells each having: — One state flip-flop with an XOR sura-of-products input — One feedback flip-flop with input coming from the I/O pin — Independent product term set,

Contextual Info: _ CY7C335 Universal Synchronous EPLD SEMICONDUCTOR Features • 100-MHz output registered operation • Twelve I/O macrocells, each having: — Registered, three-state I/O pins — Input and output register clock se­ lect multiplexer

AS7C33256NTD32A

Abstract: AS7C33256NTD36A AS7C33256PFD32A AS7C33256PFD36A AS7C33256PFS32A AS7C33256PFS36A
Contextual Info: April 2002 Preliminary 7C33256PFD32A 7C33256PFD36A 3.3V 256K x 32/36 pipeline burst synchronous SRAM Features • Organization: 262,144 words × 32 or 36 bits • Fast clock speeds to 166 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.5/3.8/4.0/5.0 ns

AS7C33232-15QC

Abstract: datasheet CI 556 ats 2300 intel 8282 AS7C33232-15TQC nt 407 f AS7C33232 MO-108 NT 407 F transistor
Contextual Info: High Performance 32Kx32 CMOS SRAM 7C33232 7C33232F 32K×32 Synchronous burst SRAM Features • Organization: 32,768 words × 32 bits • Fully synchronous pipelined operation • Flow-through option F version • Fast clocking speed: 100/75/66/60 MHz

cy7c9101

Abstract: CY2901 CY7C190 PLD20RA10 CY2149 CY7C122 CY7C148 CY7C149 CY7C150 22V10-Macrocell
Contextual Info: Military Product Selector Guide Static RAMs Size Organization 64 64 1K 1K 4K 4K 4K 4K 4K 8K 8K 16K 16K 16K 16K 16K 16K 16K 16K 16K 32K 32K 32K 32K 32K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 256K 256K 256K 256K 256K 256K 256K 1M 1M

3232F-7

Abstract: PQFP dimension intel MI-003 pqfp 14x20 100pin
Contextual Info: H igh Perform ance 32KX32 CM O S SRAM 7C33232F 3 2 K X 3 2 Synchronous burst SRA M Preliminary information Features • • • • • • • • Organization: 32,768 words x 32 bits Fully synchronous pipelined operation Flow-through or pipelined Fast clocking speed: 1 0 0 /7 5 /6 6 MHz

CY7C330-50TMB

Abstract: CY7C330 7C330
Contextual Info: CY7C330 '# C Y P R E S S Features • TVelve I/O macrocells each having: — registered, three-state I/O pins — input register clock select multi­ plexer — feed back multiplexer — output enable OE multiplexer • All twelve macrocell state registers

cy7c330

Contextual Info: CY7C330 CYPRESS SEMICONDUCTOR CMOS Programmable Synchronous State Machine Features • 256 product terms— 32 per pair of macro cells, variable distribution 12 I /O macro cells each having: — registered, three-state I /O pins — input register clock select

D-A53

Abstract: 14l8 PALC22 cypress 22V10 22V10
Contextual Info: CYPRESS SEMICONDUCTOR , P L D Programming Information Introduction Programmable Technology P L D s o r P ro g ram m ab le Logic Devices provide an a ttra c t­ ive altern ativ e to logic im plem ented w ith discrete devices. Because th e p rim ary requirem ents for this logic has been to

7c332-25

Contextual Info: This is an abbreviated datasheet. Contact a Cypress representative for complete specifications. For new designs, please refer to the CY7C335. 7C332 Registered Combinatorial EPLD Features Logic Block Diagram O E /1,2 In Ito Ig I / O , l/ O 10 I/O 9 l/O e