7C33 Search Results

AS7C33128PFS32A-166TQC

Abstract: AS7C33128NTD36A AS7C33128PFD32A AS7C33128PFD36A AS7C33128PFS32A AS7C33128PFS36A TMS320C6X 7C33128PFS32A 7C33128PFS36A
Contextual Info: January 2001 Preliminary Information 7C33128PFS32A 7C33128PFS36A 3.3V 128K X 32/36 pipeline burst synchronous SRAM Features • Organization: 131,072 words x 32 or 36 bits • Fast clock speeds to 166 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.5/3.8/4.0/5.0 ns

CC186

Abstract: CY7C3387P-1AI CY7C3387P-0AC CY7C3387P-0AI CY7C3387P-1AC
Contextual Info: 7c3387a/8a: March 2, 1995 Revision: October 6, 1995 PRELIMINARY UltraLogict Very High Speed 8K Gate CMOS FPGA Ċ 16Ćbit counter operating at 80 MHz Features D Very high speed Ċ Loadable counter frequencies greater than 80 MHz Ċ ChipĆtoĆchip operating frequencies

C3357

Abstract: c3358 CERAMIC LEADLESS CHIP CARRIER diode c335 c3356 c3355 C335 CY7C335-66PC CY7C335 C3354
Contextual Info: fax id: 6018 1CY 7C33 5 7C335 Universal Synchronous EPLD Features — 2-ns input set-up and 9-ns output register clock to output • 100-MHz output registered operation • Twelve I/O macrocells, each having: — Registered, three-state I/O pins — 10-ns input register clock to state register clock

CY7C330

Contextual Info: fax id: 6019 1CY 7C33 0 7C330 CMOS Programmable Synchronous State Machine • 66-MHz operation — 3-ns input set-up and 12-ns clock to output Features • Twelve I/O macrocells each having: — registered, three-state I/O pins — 15-ns input register clock to state register clock

Contextual Info: 7c33805: October 9, 1995 Revision: October 25, 1995 ADVANCED INFORMATION Ultra338005 UltraLogict Very High Speed 5K Gate 3.3V CMOS FPGA D Robust routing resources Features D Full 3.3V operation D Very high speed D D D D D D Ċ Loadable counter frequencies

Contextual Info: March 2001 7C33128PFS32A 7C33128PFS36A 3.3V 128K X 32/36 pipeline burst synchronous SRAM Features • Organization: 131,072 words x 32 or 36 bits • Fast clock speeds to 166 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.5/3.8/4.0/5.0 ns • Fast OE access time: 3.5/3.8/4.0/5.0 ns

CY7C3381A-0JC

Abstract: CY7C3381A-1JC CY7C3381A-1JI
Contextual Info: 7C3381A: Tuesday, October 5, 1993 Revision: October 9, 1995 7C3381A 7C3382A UltraLogict 3.3V High Speed 1K Gate CMOS FPGA Features D Very high speed D D D D D D Functional Description Ċ PC and workstation platforms D Extensive 3rd party tool support Ċ Loadable counter frequencies

Contextual Info: 7c33816: October 11, 1995 Revision: October 25, 1995 ADVANCED INFORMATION Ultra338016 UltraLogict Very High Speed 16K Gate 3.3V CMOS FPGA Features D Full 3.3V operation D Very high speed D D D D D D D Ċ Loadable counter frequencies greater than 100 MHz Ċ ChipĆtoĆchip operating frequencies

Contextual Info: 7c33807: October 9, 1995 Revision: October 25, 1995 Ultra338007 ADVANCED INFORMATION UltraLogict Very High Speed 3.3V 7K Gate CMOS FPGA D Robust routing resources Features D True 3.3V operation D Very high speed D D D D D D Ċ Loadable counter frequencies

Contextual Info: 7c33803: October 20, 1995 Revision: October 25, 1995 Ultra338003 ADVANCED INFORMATION UltraLogict Very High Speed 3K Gate 3.3V CMOS FPGA D Robust routing resources Features D Full 3.3V operation D Very high speed D D D D D D Ċ Loadable counter frequencies

Contextual Info: 7c338020: Wednesday, September 6, 1995 Revision: October 25, 1995 ADVANCED INFORMATION UltraLogict Very High Speed 20K Gate 3.3V CMOS FPGA Features D Full 3.3V operation D Very high speed D D D D D D Ultra338020 D Ċ Loadable counter frequencies greater than 100 MHz

RQW 130

Abstract: tlOH-tm33X ELLS 110 CY7C331
Contextual Info: i*bE ]> CYPRESS SEMICONDUCTOR B 256*^1.2 DDQ7Q5Q 7 Q C Y P c t 7C33i CYPRESS SEMICONDUCTOR Asynchronous Registered EPLD Features • Tnelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — O ne feedback flip-flop with input

7c331

Abstract: c33115
Contextual Info: 7C331:1/92 Revision: December 1992 fax id: 6016 7C331 V CYPRESS Asynchronous Registered EPLD • Low power Features — 90 mA typical lcc quiescent • Twelve I/O macro cel Is each having: — One state flip-flop with an XOR sum-of-products input — 180 mA lcc maximum

C3317

Abstract: CY7C331 C331 C3311 7c331
Contextual Info: 7C331: 1/92 Revision: Wednesday, January 12, 1994 7C331 Asynchronous Registered EPLD Features D Twelve I/O macrocells each having: One state flipĆflop with an XOR sumĆofĆproducts input One feedback flipĆflop with input coming from the I/O pin Independent product term set,

antifuse programmable cell

Contextual Info: 7c33812: October 9, 1995 Revision: October 25, 1995 ADVANCED INFORMATION Ultra338012 UltraLogict Very High Speed 12K 36K Gate 3.3V CMOS FPGA D Robust routing resources Features D Full 3.3V operation D Very high speed D D D D D D Ċ Loadable counter frequencies

7C335

Abstract: C3355 CY7C335 7c332 83HM
Contextual Info: 7c335: 7/16/91 Revision: Thursday, January 13, 1994 7C335 Universal Synchronous EPLD Features D 100ĆMHz output registered operation D Twelve I/O macrocells, each having: Ċ Registered, threeĆstate I/O pins Ċ Input and output register clock seĆ lect multiplexer

L496D

Abstract: 9l reset CY7C331 ST L11922 0423-J
Contextual Info: 7C331 -W C Y P R E S S Asynchronous Registered EPLD Features • TWelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coining from the I/O pin — Independent product term set,

CY7C3381A

Abstract: CY7C3381A-0JC CY7C3381A-0JI CY7C3381A-XJC CY7C3382A CY7C3384A CY7C3385A 00252-B
Contextual Info: 7C3381A 7C3382A CYPRESS Features • Very high speed — Loadable counter frequencies greater than SO MHz — Chip-to-chip operating frequencies up to 60 MHz • Unparalleled FPGA performance for counters, data path, state machines, arithmetic, and random logic

Contextual Info: 7C330 C Y P R E S S •0 Features • Twelve I/O macrocells each having: — registered, three-state I/O pins — input register clock select multi­ plexer — feed back multiplexer — output enable OE multiplexer • All twelve macrocell state registers

Contextual Info: Asynchronous Registered EPLD 13 inputs, 12 feedback VO pins, plus 6 shared I/O macrocell feedbacks for a total of 31 true and complementary inpnts High speed: 20 ns maximum tpo Security bit Space-saving 28-pin slim-line DIP package; also available in 28-pin

Contextual Info: 7C3381A 7C3382A 5r CYPRESS Features • Very high speed — Loadable counter frequencies greater than SO MHz — Chip-to-chip operating frequencies up to 60 MHz UltraLogic 3.3V High Speed IK Gate CMOS FPGA — PC and workstation platforms Functional Description

256K x 8 SRAM CY7C128A SRAM

Abstract: 5962-86705 PLD28 5962-89935 pld20ra10 5962-89598 CY7C132 cy7c291 PLD20RA PLDC20G10
Contextual Info: Military Product Selector Guide Static RAMs Size Organization Pins DIP SMD Number Part Number Speed (ns) ICC/ISB/ICCDR (mA @ ns) 883 Availability 1K 256 x 4 22 CY7C122 5962-88594 tAA = 25, 35 90 @ 25 Now 4K 1K x 4—Separate I/O 24S CY7C150 5962-88588 tAA = 25

1151a1

Contextual Info: 56 12 34 1 1234251 1 567839ABCDEBD69FBD33C3 3 1 1 3 1  39!1!" 3 1 .1 .80A1 F1 1 511 6551 51 BCD1 -F461 .1 .80A1 1 751 F561 561 51 51 65451 51 261 BCD81 9F1 1 95-1 561 61 91 691 :F1

7c331-35

Contextual Info: s :^é= , 7C331 •jS QYPRESS -■ W SEMICONDUCTOR Asynchronous Registered EPLD Features • TVelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coining from the I/O pin — Independent product term set,