7C331 Search Results

AS7C33128PFS32A-166TQC

Abstract: AS7C33128NTD36A AS7C33128PFD32A AS7C33128PFD36A AS7C33128PFS32A AS7C33128PFS36A TMS320C6X 7C33128PFS32A 7C33128PFS36A
Contextual Info: January 2001 Preliminary Information 7C33128PFS32A 7C33128PFS36A 3.3V 128K X 32/36 pipeline burst synchronous SRAM Features • Organization: 131,072 words x 32 or 36 bits • Fast clock speeds to 166 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.5/3.8/4.0/5.0 ns

Contextual Info: March 2001 7C33128PFS32A 7C33128PFS36A 3.3V 128K X 32/36 pipeline burst synchronous SRAM Features • Organization: 131,072 words x 32 or 36 bits • Fast clock speeds to 166 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.5/3.8/4.0/5.0 ns • Fast OE access time: 3.5/3.8/4.0/5.0 ns

7c331

Abstract: c33115
Contextual Info: 7C331:1/92 Revision: December 1992 fax id: 6016 7C331 V CYPRESS Asynchronous Registered EPLD • Low power Features — 90 mA typical lcc quiescent • Twelve I/O macro cel Is each having: — One state flip-flop with an XOR sum-of-products input — 180 mA lcc maximum

C3317

Abstract: CY7C331 C331 C3311 7c331
Contextual Info: 7C331: 1/92 Revision: Wednesday, January 12, 1994 7C331 Asynchronous Registered EPLD Features D Twelve I/O macrocells each having: One state flipĆflop with an XOR sumĆofĆproducts input One feedback flipĆflop with input coming from the I/O pin Independent product term set,

L496D

Abstract: 9l reset CY7C331 ST L11922 0423-J
Contextual Info: 7C331 -W C Y P R E S S Asynchronous Registered EPLD Features • TWelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coining from the I/O pin — Independent product term set,

256K x 8 SRAM CY7C128A SRAM

Abstract: 5962-86705 PLD28 5962-89935 pld20ra10 5962-89598 CY7C132 cy7c291 PLD20RA PLDC20G10
Contextual Info: Military Product Selector Guide Static RAMs Size Organization Pins DIP SMD Number Part Number Speed (ns) ICC/ISB/ICCDR (mA @ ns) 883 Availability 1K 256 x 4 22 CY7C122 5962-88594 tAA = 25, 35 90 @ 25 Now 4K 1K x 4—Separate I/O 24S CY7C150 5962-88588 tAA = 25

7c331-35

Contextual Info: s :^é= , 7C331 •jS QYPRESS -■ W SEMICONDUCTOR Asynchronous Registered EPLD Features • TVelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coining from the I/O pin — Independent product term set,

7c471

Abstract: 7C241 TNR 390 363 043 100 0 7C221K 7C361K 7C221
Contextual Info: TNR C SERIES ● Chip Type For Direct Surface Mounting 5C and 7C Type Model Number TNR5C220K TNR5C270K TNR5C330K TNR5C390K TNR5C470K TNR5C560K TNR5C680K TNR5C820K TNR5C101K TNR5C121K TNR5C151K TNR5C181K TNR5C201K TNR5C221K TNR5C241K TNR5C271K TNR7C220K

7C241

Abstract: 7c471 7C121 7C820K 7C221 7C390K 6861K 90K110 5C56 12C-390K
Contextual Info: METAL OXIDE VARISTORS TNR Chip Type For Direct Surface Mounting 5C and 7C Type ?RATINGS Operating Temperature Range: -40K+125C Storage Temperature Range: -50K+150C Maximum Applied Voltage (Continuous) AC. (Vrms) DC. (V) 18 14 22 17 26 20 30 25 37 30 44

c22v10

Abstract: C331M cypress FLASH370 device PAL22V10C-10JC pack1076 16L8 16R4 16R6 CY7C371 c20g
Contextual Info: Simulation of Cypress CPLDs with Mentor's QuickSim II Simulation of Cypress CPLDs and smaller proĆ grammable logic devices in the Mentor Graphics environment is possible without the need for purĆ chasing third party simulation models. Designs ranging the entire density span of Cypress programĆ

C3317

Abstract: L1190 CY7331
Contextual Info: Asynchronous Registered EPLD Features • TWelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coming from the I/O pin — Independent product term set, reset, and clock inputs on all

*7C471

Abstract: 7c471 7C241 7C221 p03 varistor TNR Varistor TNR9C271K 9C33
Contextual Info: TNR C SERIES ◆ Taping Specification ● The Specifications for TNR C Series B W F E FD0 T FD1 A P1 P3 T2 A Size Code 5C-A 5C-B 7C 9C 12C B P0.1 6.9 6.85 8.3 10.85 12.5 P2 W P0.1 10.4 8.05 10.6 13.0 16.3 Direction of feed F E P0.3 P0.1 16.0 7.5 24.0 Dimensions mm

cy7c9101

Abstract: CY2901 CY7C190 PLD20RA10 CY2149 CY7C122 CY7C148 CY7C149 CY7C150 22V10-Macrocell
Contextual Info: Military Product Selector Guide Static RAMs Size Organization 64 64 1K 1K 4K 4K 4K 4K 4K 8K 8K 16K 16K 16K 16K 16K 16K 16K 16K 16K 32K 32K 32K 32K 32K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 256K 256K 256K 256K 256K 256K 256K 1M 1M

PLD28

Abstract: 22V10-Macrocell 5962-86705 5962-89598 cy7c291 PLDC20G10 CY6116A CY7C128A CY7C168A CY7C185A
Contextual Info: Military Product Selector Guide Static RAMs Size Organization Pins DIP SMD Number Part Number Speed (ns) ICC/ISB/ICCDR (mA @ ns) Availability 16K 2K x 8—CS Power-Down 24S CY7C128A 5962-89690 tAA = 20, 25 125 @ 20 Now 16K 2K x 8—CS Power-Down 24S CY7C128A

EI24

Abstract: GI05 st C331 n 332 ab EI-24
Contextual Info: _ ~ 2 r 7C331 •^CYPRESS Features • 13 inputs, 12 feedback I/O pins, plus 6 • Twelve I/O macrocells each having: — One stale flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coming from the I/O pin — Independent product term set,

7C471

Abstract: 12C15 7C241 *7C471 TNR 390 7C361 TNR5C271K
Contextual Info: METAL OXIDE VARISTORS TNR Chip Type For Direct Surface Mounting 5C and 7C Type ?RATINGS Operating Temperature Range: -40K+125C Storage Temperature Range: -50K+150C Maximum Applied Voltage (Continuous) AC. (Vrms) DC. (V) 18 14 22 17 26 20 30 25 37 30 44

CY6116A

Abstract: CY7C128A CY7C168A CY7C185A CY7C198 CY7C199 CY37128 5962-85525 84036 Product Selector Guide
Contextual Info: Military Product Selector Guide Static RAMs Size Organization Pins DIP Part Number SMD Number Speed (ns) ICC/ISB/ICCDR (mA @ ns) Availability 16K 2K x 8—CS Power-Down 24S CY7C128A 5962-89690 tAA = 20, 25 125 @ 20 Now 16K 2K x 8—CS Power-Down 24S CY7C128A

7c471

Abstract: 7C221 7C241 7C471K 12C241K 9C331K TNR12C270K TNR12C330K 7C241K 7C431K
Contextual Info: TNR C SERIES ● Chip Type For Direct Surface Mounting 5C and 7C Type Model Number Maximum Applied Voltage (Continuous) TNR5C220K TNR5C270K TNR5C330K TNR5C390K TNR5C470K TNR5C560K TNR5C680K TNR5C820K TNR5C101K TNR5C121K TNR5C151K TNR5C181K TNR5C201K TNR5C221K

2SUR

Abstract: CY7C331 L1190 C3317
Contextual Info: 7C331 ¿F C Y P R E S S Features • TWelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coining from the I/O pin — Independent product term set, reset, and clock inpnts on all

Contextual Info: 7C331 CYPRESS ~ = SEMICONDUCTOR Asynchronous Registered EPLD Functional Description IWelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input T h e 7C331 is the m ost versatile PLD available for asynchronous designs. C en­

RQW 130

Abstract: tlOH-tm33X ELLS 110 CY7C331
Contextual Info: i*bE ]> CYPRESS SEMICONDUCTOR B 256*^1.2 DDQ7Q5Q 7 Q C Y P c t 7C33i CYPRESS SEMICONDUCTOR Asynchronous Registered EPLD Features • Tnelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — O ne feedback flip-flop with input

22V10-Macrocell

Abstract: Product Selector Guide PLD20RA10 5962-93112 28s40 CY7C408
Contextual Info: Military Product Selector Guide Static RAMs Size Organization Pins DIP Part Number SMD Number 16K 2K x 8—CS Power-Down 24S CY7C128A 16K 2K x 8—CS Power-Down 24 CY6116A 64K 8K x 8—CS Power-Down 28S CY7C185A 5962-38294 64K 8K x 8—CS Power-Down 28S

5962L0053605VYC

Abstract: 5962-9069204QXA ATMEL 302 24C16 UT9Q512E-20YCC MOH0268D UT54ACS164245SEIUCCR Z085810 5962-9762101Q2A UT28F256QLET-45UCC 5962R0250401KXA
Contextual Info: NOT MEASUREMENT SENSITIVE MIL-HDBK-103AJ 19 SEPTEMBER 2011 SUPERSEDING MIL-HDBK-103AH 28 MARCH 2011 DEPARTMENT OF DEFENSE HANDBOOK LIST OF STANDARD MICROCIRCUIT DRAWINGS This handbook is for guidance only. Do not cite this document as a requirement. AMSC N/A

Contextual Info: 7C331 s CYPRESS Asynchronous Registered EPLD SEMICONDUCTOR Features Product Characteristics 13 inputs, 12 feedback I /O pins, plus 6 shared I /O macrocell feedbacks for a total of 31 true and complementary inputs • 12 I /O macrocells each having: — One state Flip-Flop with an