352PIN Search Results

CHIP EPROM AE12

Abstract: spru402 ST2328
Contextual Info: TMS320C6201 FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR SPRS051G – JANUARY 1997 – REVISED NOVEMBER 2000 D High-Performance Fixed-Point Digital D D D D D D Signal Processor DSP TMS320C6201 – 5-ns Instruction Cycle Time – 200-MHz Clock Rate – Eight 32-Bit Instructions/Cycle

C6701

Contextual Info: TMS320C6701 FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR SPRS067E – MAY 1998 – REVISED MAY 2000 D Highest Performance Floating-Point Digital D D D D D Signal Processor DSP TMS320C6701 – 8.3-, 6.7-, 6-ns Instruction Cycle Time – 120-, 150-, 167-MHz Clock Rate

c6000 flash

Abstract: TMDX320006211
Contextual Info: TMS320C6211 FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR TMS320C6711 FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR SPRS073C – AUGUST 1998 – REVISED JUNE 2000 D D D Processors DSPs Fixed-Point: TMS320C6211 Floating-Point: TMS320C6711 – 10-, 6.7-ns Instruction Cycle Time

TEXAS INSTRUMENTS, Mold Compound, CSP

Contextual Info: SM320C6202ĆEP FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR SGUS044–JULY 2003 D Controlled Baseline D D D D D D D D D D 3M-Bit On-Chip SRAM – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –40°C to 105°C Enhanced Diminishing Manufacturing

Contextual Info: SM320C6711ĆEP, SM320C6711BĆEP, SM320C6711CĆEP, SM320C6711DĆEP FLOATINGĆPOINT DIGITAL SIGNAL PROCESSORS SGUS054A − AUGUST 2004 − REVISED SEPTEMBER 2005 D Controlled Baseline D D D D D D D D L1/L2 Memory Architecture − One Assembly/Test Site, One Fabrication

352-PIN

Abstract: TMS320C6202 TMS320C6202B
Contextual Info: TMS320C6202, TMS320C6202B FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS104I - OCTOBER 1999 - REVISED MARCH 2004 D High-Performance Fixed-Point Digital D D D D D D Signal Processors DSPs - TMS320C62x - 5-, 4-, 3.33-ns Instruction Cycle Time - 200-, 250-, 300-MHz Clock Rate

00XXX001

Abstract: BA 5979 R15C3 OR3T125 OR3T20 OR3T30 OR3T55 PT10 PT11 PT12
Contextual Info: Data Sheet November 2006 ORCA Series 3C and 3T Field-Programmable Gate Arrays Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Baseline FPGA family used in Series 3+ FPSCs field programmable system chips which combine FPGA logic

Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT µPD98431 10/100 Mbps Ethernet TM CONTROLLER DESCRIPTION The µPD98431 is a 10/100 Mbps Ethernet controller having eight Media Access Control MAC ports conforming to IEEE 802.3 and IEEE 802.3u. Each port can store 1 packet of receive data since each port has a 2 KB receive FIFO. This can reduce the

Contextual Info: TMS320C6701 FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR SPRS067F − MAY 1998 − REVISED MARCH 2004 D Highest Performance Floating-Point Digital D D D D D Signal Processor DSP TMS320C6701 − 8.3-, 6.7-, 6-ns Instruction Cycle Time − 120-, 150-, 167-MHz Clock Rate

Contextual Info: TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C − OCTOBER 2000 − REVISED MARCH 2004 D High-Performance Fixed-Point Digital D D D D D Signal Processor DSP − TMS320C6204 − 5-ns Instruction Cycle Time − 200-MHz Clock Rate − Eight 32-Bit Instructions/Cycle

Contextual Info: SM320C6201-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SGUS041A - MAY 2003 - REVISED JANUARY 2004 D Controlled Baseline D D D D D D D - One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of -40°C to 105°C Enhanced Diminishing Manufacturing

Contextual Info: SM320C6701ĆEP, SM320C6701MECHĆEP FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR SGUS042A − MAY 1998 − REVISED APRIL 2004 D Controlled Baseline D D D D D D D D 1M-Bit On-Chip SRAM − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance up to

Contextual Info: SM320C6201-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SGUS041A - MAY 2003 - REVISED JANUARY 2004 D Controlled Baseline D D D D D D D - One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of -40°C to 105°C Enhanced Diminishing Manufacturing

Contextual Info: SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS SGUS017H - OCTOBER 1993 - REVISED OCTOBER 2001 D D D D D D D D D D D D D SMJ: QML Processing to MIL-PRF-38535 SM: Standard Processing TMP: Commercial Level Processing TAB Operating Temperature Ranges: - Military M -55°C to 125°C

Contextual Info: SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS SGUS017H - OCTOBER 1993 - REVISED OCTOBER 2001 D D D D D D D D D D D D D SMJ: QML Processing to MIL-PRF-38535 SM: Standard Processing TMP: Commercial Level Processing TAB Operating Temperature Ranges: - Military M -55°C to 125°C

Contextual Info: SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS SGUS017H – OCTOBER 1993 – REVISED OCTOBER 2001 D D D D D D D D D D D D D SMJ: QML Processing to MIL–PRF–38535 SM: Standard Processing TMP: Commercial Level Processing TAB Operating Temperature Ranges:

Contextual Info: SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS SGUS017H - OCTOBER 1993 - REVISED OCTOBER 2001 D D D D D D D D D D D D D SMJ: QML Processing to MIL-PRF-38535 SM: Standard Processing TMP: Commercial Level Processing TAB Operating Temperature Ranges: - Military M -55°C to 125°C

APA600

Abstract: AA23 APA075 APA1000 APA150 APA300 APA450 APA750
Contextual Info: ProASICPLUS Flash Family FPGAs Package Pin Assignments 100-Pin TQFP 1 100 100-Pin TQFP Note For Package Manufacturing and Environmental information, visit the Package Resource center at . v5.8 2-1 ProASICPLUS Flash Family FPGAs

729-Pin

Abstract: Axcelerator FPGAs AX125 IO126PB3F11 AG18 FBGA 896 896-Pin Axcelerator Family FPGAs
Contextual Info: Axcelerator Family FPGAs Package Pin Assignments 180-Pin CSP A1 Ball Pad Corner 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P Figure 3-1 • 180-Pin CSP Bottom View Note For Package Manufacturing and Environmental information, visit Resource center at

loadable counter

Contextual Info: ADVANCED INFORMATION m .7 Ultra38016 C Y P R E S S UltraLogic Very High Speed 16K Gate CMOS FPGA Features • Very high speed — Loadable counter frequencies greater than 185 MHz — Chip-to-chip operating frequencies up to 135 MHz — Input + logic cell + output delays

Contextual Info: CYPRESS Features • Very high speed — Loadable counter frequencies greater than 185 MHz — Chip-to-chip operating frequencies up to 135 MHz — Input + logic cell + output delays under 5.5 ns • Unparalleled FPGA performance for counters, data path, state machines,

EXCCET103

Abstract: INVERTER 20kW SPRU011 C6701 MC68360 MPC860 PCI9050 TMS320C6000 TMS320C6201 TMS320C6701
Contextual Info: TMS320C6701 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS067F − MAY 1998 − REVISED MARCH 2004 D Highest Performance Floating-Point Digital D D D D D Signal Processor DSP TMS320C6701 − 8.3-, 6.7-, 6-ns Instruction Cycle Time − 120-, 150-, 167-MHz Clock Rate

Contextual Info: TMS320C6712, TMS320C6712C FLOATINGĆPOINT DIGITAL SIGNAL PROCESSORS SPRS148D – AUGUST 2000 – REVISED MARCH 2003 D Best Price/Performance Digital Signal D D D D D Processors DSPs : TMS320C67x (TMS320C6712, TMS320C6712C) – Eight 32-Bit Instructions/Cycle

Contextual Info: TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D FLOATINGĆPOINT DIGITAL SIGNAL PROCESSORS SPRS088M − FEBRUARY 1999 − REVISED FEBRUARY 2005 D Excellent-Price/Performance Floating-Point D D D D D Digital Signal Processors DSPs : TMS320C67x (C6711, C6711B, C6711C,