7B174 Search Results

Contextual Info: CY7B180 CY7B181 s CYPRESS SEMICONDUCTOR 4K x 18 Cache Tag Features • Can be used as 4K x 18 SRAM • Supports 66-MHz cache for all major high-speed processors Functional Description T he CY7B180 and CY7B181 are high-perform ance B iC M O S cache tag R A M s orga­

7b174

Contextual Info: PRELIM INARY CY7B173 7B174 r^ y p p u c Q Features • Supports 50-MHz cache systems • 32K by 9 common I/O • BiCMOS for optimum speed/power • 14-ns access delay clock to output • Ttoo-bit wraparound counter support­ ing the 486 burst sequence (7B173)

Contextual Info: PRELIMINARY CYPRESS SEMICONDUCTOR F eatures • S u p p o rts 66-M H z P e n tiu m lu C PU ca ch e system s • A vailab le in stan d ard PLC C /LC C CY7B173A 7B174A 32K x 9 Synchronous Cache R/W RAM • D irect in terface w ith the p ro cesso r and extern al ca ch e con tro ller

11ax

Abstract: 80486 microprocessor pin out diagram
Contextual Info: PRELIMINARY CYPRESS SEMICONDUCTOR Features 32K x 9 Synchronous Cache R/W RAM • D irect interface with the processor and external cache controller Supports 66-M Hz Pentium " CPU cache systems • TWo complementary synchronous chip enables Available in standard PLCC/LCC

Contextual Info: / u i f o / t n . i£ /o /9 U Revision: Monday, January 11,1993 IC Y P *•*% * IM PRELIM INARY CYPRESS ~ — . SEMICONDUCTOR Features • Supports 66-MHz cache systems • Available in PQFP with 25-Mil lead pitch • BiCMOS for optimum speed/power • 9-ns access delay clock to output

intel 80486

Abstract: CY7B174 44-Square block diagram of processor 80486 80486 circuit AADS
Contextual Info: CY7B173 7B174 CYPRESS SEMICONDUCTOR Features • S u p p orts 50-M H z ca c h e system s • 3 2 K by 9 com m on I/O • B iC M O S for op tim u m speed /p ow er • 14-ns a ccess delay clock to ou tpu t • Two-bit w rap arou nd cou n ter su p p ort­

7H17

Contextual Info: AD VAN C ED IN FO R M A TIO N CYPRESS SEMICONDUCTOR 32,768 x 9 Synchronous Cache R/W RAM Features • Asynchronous output enable • 32K by 9 common I/O • 44-pin PLCC and LCC • BiCMOS for optimum speed/power Functional Description • 14-ns access delay clock to output

Contextual Info: CY7B173 7B174 CYPRESS = SEMICONDUCTOR • Supports 50-MHz cache systems • Asynchronous output enable • 32K by 9 common I/O Functional Description • BiCMOS for optimum speed/power 14-ns access delay clock to output • Two-bit wraparound counter support­

27BV040

Abstract: MIL-M-38535 6a9618
Contextual Info: PAGE 1 OF 7 ATMEL CORPORATION Tel: 408 441-0311 Fax:(408)436-4200 AT-27BV040 EPROM RELIABILITY DATA - 125°C OPERATING LIFE TEST (PLASTIC) - 150°C RETENTION BAKE (PLASTIC) - 85°C/85% RELATIVE HUMIDITY OPERATING LIFE TEST - 15 PSIG PRESSURE POT - EXTENDED TEMPERATURE CYCLING

Contextual Info: /D1/J/4A: iü/e/90 Revision: Monday, January 11,1993 -W £3 *993 PRELIMINARY r^ Y P P F Q c — SEMICONDUCTOR 32K x 9 Synchronous Cache R/W RAM • IWo complementary synchronous chip selects • Asynchronous output enable Features • Supports 66-MHz cache systems