7B173 Search Results

7b174

Contextual Info: PRELIM INARY 7B173 CY7B174 r^ y p p u c Q Features • Supports 50-MHz cache systems • 32K by 9 common I/O • BiCMOS for optimum speed/power • 14-ns access delay clock to output • Ttoo-bit wraparound counter support­ ing the 486 burst sequence (7B173)

Contextual Info: PRELIMINARY CYPRESS SEMICONDUCTOR F eatures • S u p p o rts 66-M H z P e n tiu m lu C PU ca ch e system s • A vailab le in stan d ard PLC C /LC C 7B173A CY7B174A 32K x 9 Synchronous Cache R/W RAM • D irect in terface w ith the p ro cesso r and extern al ca ch e con tro ller

11ax

Abstract: 80486 microprocessor pin out diagram
Contextual Info: PRELIMINARY CYPRESS SEMICONDUCTOR Features 32K x 9 Synchronous Cache R/W RAM • D irect interface with the processor and external cache controller Supports 66-M Hz Pentium " CPU cache systems • TWo complementary synchronous chip enables Available in standard PLCC/LCC

61a17

Abstract: E11AB BFE 81A
Contextual Info: 123456789 1 2ABBCD91BCEFE9ECBE1 9 1 92DBB9 1 BB9BCAE9 716351B7B7978916789ABC91871787BA81 977E1 81 8A1 D !1 "71 981 BAE799ABF1 71 6351 91 79871 A1 #B81 1 7B$AB"8E71 977E1D !1$7%B791A1EA919789&71 7"#771 81

Contextual Info: / u i f o / t n . i£ /o /9 U Revision: Monday, January 11,1993 IC Y P *•*% * IM PRELIM INARY CYPRESS ~ — . SEMICONDUCTOR Features • Supports 66-MHz cache systems • Available in PQFP with 25-Mil lead pitch • BiCMOS for optimum speed/power • 9-ns access delay clock to output

intel 80486

Abstract: CY7B174 44-Square block diagram of processor 80486 80486 circuit AADS
Contextual Info: 7B173 CY7B174 CYPRESS SEMICONDUCTOR Features • S u p p orts 50-M H z ca c h e system s • 3 2 K by 9 com m on I/O • B iC M O S for op tim u m speed /p ow er • 14-ns a ccess delay clock to ou tpu t • Two-bit w rap arou nd cou n ter su p p ort­

7H17

Contextual Info: AD VAN C ED IN FO R M A TIO N CYPRESS SEMICONDUCTOR 32,768 x 9 Synchronous Cache R/W RAM Features • Asynchronous output enable • 32K by 9 common I/O • 44-pin PLCC and LCC • BiCMOS for optimum speed/power Functional Description • 14-ns access delay clock to output

Contextual Info: 7B173 CY7B174 CYPRESS = SEMICONDUCTOR • Supports 50-MHz cache systems • Asynchronous output enable • 32K by 9 common I/O Functional Description • BiCMOS for optimum speed/power 14-ns access delay clock to output • Two-bit wraparound counter support­

Contextual Info: /D1/J/4A: iü/e/90 Revision: Monday, January 11,1993 -W £3 *993 PRELIMINARY r^ Y P P F Q c — SEMICONDUCTOR 32K x 9 Synchronous Cache R/W RAM • IWo complementary synchronous chip selects • Asynchronous output enable Features • Supports 66-MHz cache systems