75122 Search Results

Contextual Info: MOS LSI TMS 3120 JC. NC; QUADRUPLE 80-BIT STATIC SHIFT REGISTERS B U L L E T IN NO . O L-S 7512267 D C to 2.5-MHz Operation R E V I S E D N O V E M B E R 1*77 1 & -PIN C E R A M I C A N D P L A S T IC D U A L -IN - L IN E P A C K A G E S T o p v j e w Configuration

SN5522

Abstract: LM75122 1N3064 8T14 LM55122J LM75122J LM75122N lm5512
Contextual Info: LM 55122/L M 75122 MS Line Drivers/Receivers L M 5 5 1 2 2 /L M 7 5 1 2 2 triple line receivers features general description The L M 5 5 1 2 2 /L M 7 5 1 2 2 are trip le line receivers designed fo r digital data transm ission w ith line • B u ilt-in in p u t threshold hysteresis

Contextual Info: MOS LSI TMS 3120 JC. NC; TMS 3121 JC, NC QUADRUPLE 80-, 64-BIT STATIC SHIFT REGISTERS B U L L E T IN DC to 2 .5 -M H z Operation NO. D L -S 7512267, M A Y 1975 16-PIN CE R A M IC A N D PLASTIC D U A L -IN -L IN E PACKAGES TOP V IE W Static Configuration

SN74S209J

Abstract: SN74S309 SN74S209 SN74S189 SN54S189J S289 S189 S201 S301 SN54S289J
Contextual Info: TTL MEMORIES SERIES 54S/74S RANDOM-ACCESS READ/WRITE MEMORIES BULLETIN NO. DL•S 7512257, MAY 1975 64 BITS 16 WORDS BY 4 BITS 'S189, 'S289 256 BITS (256 WORDS BY 1 BIT) 'S201, 'S301 1024 BITS (1024 WORDS BY 1 BIT) SN74S209,SN74S309 CE 16 VCC ADA 16 VCC 16

SN74370

Abstract: SN54187 SN5488A SN74187 SN7488A 88a1 S271 equivalent
Contextual Info: TTL MEMORIES SERIES 54/74, 54S/74S READ-ONLY MEMORIES BULLETIN NO. DL•S 7512259, MAY 1975 Mask-Programmed Memories That Can Replace PROMs • Full On-Chip Decoding and Fast Chip Select s Simplify System Decoding • • All Schottky-Clamped ROMs Offer -Choice of 3-State or Open-Collector Outputs

SN10000

Abstract: SN10139 SN10139J SN10140 SN10142 SN10144 SN10145 SN10145JE SN10147 SN10148
Contextual Info: SERIES SN10000 MEMORIES Eel INTEGRATED CIRCU ITS BULLETIN NO. DL-S 7512255, MAY 1975 • Full On-Chip Address Decoding and Output-Sense Amplification • Constant Current Drain Over a Wide Supply Voltage Range • Logic Levels Compatible with Series SN10000 Logic Levels

TA 55122

Abstract: ta55122 8T14 75122 8T24
Contextual Info: MA8T14 • 55122 • 75122 T R I P L E L IN E R E C E I V E R S F A IR C H IL D LINEAR IN T E G R A T E D C IR C U IT S G E N E R A L D E S C R IP T IO N — T h e 5 5 1 2 2 /7 5 1 2 2 / ^ A 8 T 1 4 T r ip le L in e R e c e iv e r is d e s ig n e d t o rece ive

8T14

Contextual Info: iuA8T14 • 55122 • 75122 TRIPLE LINE RECEIVERS F A IR C H IL D LINEAR IN T E G R A T E D C IR C U IT S G E N E R A L D E S C R IP T IO N - The 55122/75122//iA8T14 Triple Line Receiver is designed to receive digital information from coaxial cable, strip line, or twisted pair single ended transmission lines. High

ECL Handbook

Abstract: mode 5 IFF 9N38 9582 Fairchild
Contextual Info: 9 61 2 9614 9616 9621 5 5 /7 5 1 0 9 5 5 /7 5 1 1 0 5 5 /7 5 1 2 1 75123 FAIRCHILD 9613 75122 INTEGRATED Diff or S in g le I Ended S ing le or Ended Diff Ended S ing le back Lim . 250 Fold- Ended back Lim 250 FoldEnded back Lim . 250 back Lim . 250 FoldEnded

TMS4063

Abstract: ql 5012 SN75370 22-PIN AD-2000
Contextual Info: TMS 4062 JL, NL; TMS 4063 JL, NL 1024-WORD BY l-BIT DYNAMIC RANDOM-ACCESS MEMORIES MOS LSI BULLETIN • 1024 x 1 Organization • Access Time . 130 ns Maximum • Cycle Time . 200 ns Maximum • Low Power Dissipation: NO. DL-S 7512272. MAY 1975 TMS 4062 JL, NL

100J

Contextual Info: MOS LSI TMS 3133 NC 1024-81T STATIC SHIFT REGISTER BULLETIN NO. DL-S 7512264, MAY 1975 • DC to 2-MHz Operation • Static Configuration • Single TTL-Compatible Clock • Inputs and Outputs Fully TTL-Compatible • Push-Pull Output Buffers • Power Supplies . 5 V, -12 V

TMS6011JC

Abstract: TMS6011 tms 6011 wls1 texas instruments uart
Contextual Info: MOS LSI TMS 6011 JC. NC ASYNCHRONOUS DATA INTERFACE UART BULLETIN NO. DL-S 7512275, MAY 1975 • • • • • • • • • • • • • • • II Transmits, Receives, and Formats Data Full-Duplex or Half-Duplex Operation Operation from DC to 200 kHz

TMS3113

Abstract: TMS3114JC
Contextual Info: MOS LSI TMS 3113 JC, NC; TMS 3114 JC, NC DUAL 133-, 128-81T STATIC SHIFT REGISTERS BULLETIN NO. DL-S 7512262. MAY 1975 • • • • • • • DC to 2-MHz Operation 16-PIN CERAMIC AND PLASTIC DUAL-IN-LiNE PACKAGES TOP VIEW Static Configuration Single TTL-Compatible Clock

TMS4030

Abstract: 40301 ci 4030 22-PIN TMS403 TMS4030JL TMS 4030
Contextual Info: MOS LSI TMS 4030 JL, NL; TMS 4030-1 JL, NL; TMS 4030-2. JL, NL 4096-81T DYNAMIC RANDOM-ACCESS MEMORIES BULLETIN NO. DL-S 7512240, FEBRUARY 1975 22-PIN CERAMIC AND PLASTIC DUAL•IN-LiNE PACKAGES TOP VIEW • 4096 x 1 Organization • 3 Performance Ranges:

tms 374

Abstract: tms 374 chip 3126 "pin compatible" 136 8PIN
Contextual Info: MOS LSI TMS 3126, 3127, 31-28, 3129, 3130, 3131, 3132 LC, NC DUAL 96-, 100-, 128-, 132-, 133-, 136-, 144-81T STATIC SHIFT REGISTERS BULLETIN NO. DL•S 7512263, MAY 1975 • DC to 2.5-MHz Operation • Static Configuration • Single TTL-Compatible Clock TO·99 HERMETICALLY SEALED PACKAGE

r08f

Contextual Info: TMS 4800 JL, NL 16384-BIT READ-ONLY MEMORY MOS LSI BULLETIN NO. DL-S 7512260, MAY 1975 24-PIN CERAMIC AND PLASTIC DUAL-IN•LlNE PACKAGES TOP VIEW • 2048 x 8 or 4096 x 4 Organization • Total TTL-Compatibility • Maximum Access Time . 700 ns VSS • Minimum Cycle Time . 1000 ns

ci 4030

Abstract: ci 4060 4060 PIN DIAGRAM TMS 4030 TMS4030 TMS4060 a5 chip 4060 18-PIN 22-PIN
Contextual Info: TMS 4030 JR, TMS 4050 JR, TMS 4060 JR SMC 4030 JR, SMC 4050 JR, SMC 4060 JR 4096-81T RANDOM-ACCESS MEMORIES MOS LSI BULLETIN NO DL-S 7512276, MAY 1975 EXTENDED TEMPERATURE RANGE AND HI-REL DEVICES • 4096 x 1 Organization • Extended Temperature Range _55° C to 85° C

digital clock notes

Abstract: 4024 N
Contextual Info: MOS LSI TMS 4 0 2 4 JC, NC 9 X 64 DIGITAL STORAGE BUFFER FIFO B U L L E T IN 6 4 Words o f 9 Bits o f Elastic Storage NO. D L -S 7512268, M AY 1975 2 8 -P IN C E R A M IC A N D P L A S T IC D U A L -IN -L IN E P A C K A G E S T T L -C o m p a tib ility on A ll Inputs

rna310

Abstract: 10-MEMORY
Contextual Info: TMS 4700 JL, NL 1024-WORD BY 8-BIT READ-ONLY MEMORY MOS LSI BULLETIN • • 1024 x 8 Organization All Inputs and Outputs NO. DL-S 7512273, MAY 1975 24•PIN CERAMIC AND PLASTIC DUAL-IN-LINE PACKAGES TOP VIEW TTL~Compatible • • • • 24 VCC Typical Power Dissipation . 310 mW

et 1103

Abstract: 1103-1 18-PIN TMS1103 1024-81T A8712 TMS 1024 1103
Contextual Info: MOS LSI TMS 1103 JL, NL; TMS 1103-1 JL, NL 1024-81T DYNAMIC RANDOM-ACCESS MEMORIES BULLETIN NO. DL-S 7512234, JANUARY 1975 • 1024 x 1-Bit Organization • Low Power Dissipation Input Interface - Fully Decoded, On-Chip Address Decode - Static Charge Protection

CD 4050 pin diagram

Abstract: TMS4050 40501 TMS 4050 NL 18-PIN 1975-REVISED ot220
Contextual Info: MOS LSI TMS 4050 Jl, Nl; TMS 4050-1 Jl, Nl; TMS 4050-2 Jl, Nl 4096-81T DYNAMIC RANDOM-ACCESS MEMORIES BULLETIN NO. DL-S 7512242, FEBRUARY 1975-REVISED MAY 1975 • • • • 4096 x 1 Organization 18-Pin 300-Mil Package Configuration Multiplexed Data Input/Output

texas 74 series TTL logic gates

Abstract: tms3417 TMS3409 TMS3417JC 3417jc 3417
Contextual Info: MOS LSI TMS 3409 JC, NC; TMS 3417 JC, NC QUADRUPLE 80-, 64-BIT DYNAMIC SHIFT REGISTERS BULLETIN NO. DL-S 7512266, MAY 1975 • 10-kHz to 5-MHz Operation • Dynamic Configuration • Single TTL-Compatible Clock 16-PIN CERAMIC AND PLASTIC DUAL-IN-LiNE PACKAGES

Contextual Info: MOS LSI TMS 3135, 3137, 3138, 3139, 3140 JC, NC 9- BY 80-, 100-, 128-, 132-" 133-BIT STATIC SHIFT REGISTERS BULLETIN NO. DL-S 7512265, MAY 1975 • DC to 1.5-MHz Operation • • Static Configuration Single TTL-Compatible Clock REC 24 Vss • Inputs and Outputs Fully TTL-Compatible

TO-99

Abstract: 75453 B1 9A TTL nand 8T13 8T14 8T23 8T24 TO99 75431
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS INTERFACE 115 55/75325 SOURCE 118 55/75432, 55/75452, 55/7562, 55/7572 116 55/75430, 55/75450, 55/75460 119 55/75433, 55/75453, 55/75463, 55/75473 121 I22 8T13, 8T23, 55/75121, 75123 8T14, 8T24, 55/75122, 75124 | Vcc I IN 8 6