74LV00 Search Results

74LV00

Abstract: 74LV00D 74LV00DB 74LV00N 74LV00PW
Contextual Info: •¿¿ms Product Specification Philips S em iconductors 74LV00 Quad 2-input NAND gate Q U IC K R EFERENCE DATA G N D = 0 V ; T ^ = 25°C; tr = t, < 2.5 ns FEA TUR ES • • • • • • • W id e operating voltage: 1.0 to 5.5 V O ptim ized for Low V oltage

Contextual Info: 74LV00 Quad 2-input NAND gate Rev. 03 — 20 December 2007 Product data sheet 1. General description The 74LV00 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC00 and 74HCT00. The 74LV00 provides a quad 2-input NAND function.

74LV00

Abstract: 74LV00D 74LV00DB 74LV00N 74LV00PW
Contextual Info: Philips Semiconductors Product Specification Quad 2-input NAND gate 74LV00 QUICK REFERENCE DATA FEATURES GND = 0 V; TOTb = 25°C; t, = t, < 2.5 ns • • • Optimized for Low Voltage applications: 1.0 to 3.6 V Accepts TTL Input levels between Vcc = 2.7 V and

74LV00

Abstract: 74LV00PW 74LV00 Philips
Contextual Info: INTEGRATED CIRCUITS 74LV00 Quad 2-input NAND gate Product specification IC24 Data Handbook Philips Semiconductors 1997 Feb 03 Philips Semiconductors Product specification Quad 2-input NAND gate 74LV00 FEATURES DESCRIPTION • Wide operating voltage: 1.0 to 5.5 V

74lvoon

Abstract: f13y 74HC,HCT00 74LV00 74LV00D 74LV00N
Contextual Info: Philips Semiconductors b3E D • bbS3T2M Quad 2-input NAND gate FEATURES 006372=1 n a p c /p h i l i p s ETT « S IC 3 Product Specification 74LV00 semicond QUICK REFERENCE DATA GND = 0 V; T ^ = 25°C; t, = t, S 2.5 ns • • • • • • Optimized for Low Voltage

74LV00

Abstract: 74lvoon 74LV00D 74LV00DB 74LV00N 74LV00PW 9121A
Contextual Info: Philips Semiconductors Product Specification Quad 2-input NAND gate FEATURES 74LV00 Q U IC K R E F E R E N C E D A T A G N D = 0 V; T ^ b = 25°C; t, = t, < 2.5 ns • O ptim ized fo r L o w Voltage ap p lica tio n s: 1.0 to 3.6 V • A c c e p ts T T L in put le v e ls

74HC00

Abstract: 74HCT00 74LV00 74LV00BQ 74LV00D 74LV00DB 74LV00N 74LV00PW JESD22-A114E 74LV001
Contextual Info: 74LV00 Quad 2-input NAND gate Rev. 03 — 20 December 2007 Product data sheet 1. General description The 74LV00 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC00 and 74HCT00. The 74LV00 provides a quad 2-input NAND function.

74LV00

Abstract: 74LV00PW MS-012AB
Contextual Info: Philips Semiconductors Product specification Quad 2-input NAND gate 74LV00 FEATURES DESCRIPTION • W id e o p e ra tin g v o lta g e : 1.0 to 5.5 V T h e 7 4 LV 00 is a lo w -v o lta g e S i-g a te C M O S d e v ic e th a t is pin an d fu n ctio n c o m p a tib le w ith 7 4 H C /H C T 0 0 .

74LV00

Abstract: 74LV00PW
Contextual Info: Philips Semiconductors Product specification Quad 2-input NAND gate 74LV00 FEATURES DESCRIPTION • W id e o p e ra tin g v o lta g e : 1.0 to 5.5 V T h e 7 4 LV 00 is a lo w -v o lta g e S i-g a te C M O S d e v ic e th a t is pin an d fu n ctio n c o m p a tib le w ith 7 4 H C /H C T 0 0 .

74LV00AS14-13

Contextual Info: 74LV00A QUADRUPLE 2-INPUT NAND GATES Description Pin Assignments The 74LV00A provides provides four independent 2-input NAND gates with standard push-pull outputs. The device is designed for operation with a power supply range of 2.0V to 5.5V. The inputs are tolerant to 5.5V allowing this device to be used in a

Contextual Info: Philips Sem iconductors Product specification Quad 2-input NAND gate 74LV00 FEATURES DESCRIPTION • Wide operating voltage: 1.0 to 5.5 V The 74LV00 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT00. • Optimized tor low voltage applications: 1.0 to 3.6 V

Contextual Info: INTEGRATED CIRCUITS 74LV00 Quad 2-input NAND gate Product specification Supersedes data of 1998 Apr 13 IC24 Data Handbook Philips Semiconductors 1998 Apr 20 PHILIPS Philips Semiconductors Product specification Quad 2-input NAND gate 74LV00 FEATURES DESCRIPTION

74LV00

Abstract: 74LV00PW
Contextual Info: INTEGRATED CIRCUITS 74LV00 Quad 2-input NAND gate Product specification Supersedes data of 1998 Apr 13 IC24 Data Handbook Philips Semiconductors 1998 Apr 20 Philips Semiconductors Product specification Quad 2-input NAND gate 74LV00 FEATURES DESCRIPTION • Wide operating voltage: 1.0 to 5.5 V

A115-A

Abstract: C101 SN54LV00A SN74LV00A
Contextual Info: SN54LV00A, 74LV00A QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS389G – SEPTEMBER 1997 – REVISED OCTOBER 2002 SN54LV00A . . . J OR W PACKAGE 74LV00A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 1B

Contextual Info: SN54LV00A, 74LV00A QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS389G – SEPTEMBER 1997 – REVISED OCTOBER 2002 SN54LV00A . . . J OR W PACKAGE 74LV00A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 1B

5555 FAIRCHILD optocoupler

Abstract: MC74HC374N 74hc14n equivalent NC7S125M5 14069 HCF4541BEY APPLICATION HCF4013BE 4026 fairchild datasheet 14543 motorola Motorola DM74LS139N
Contextual Info: R E L I A B L E . L O G I C . I N N O V A T I O N . Logic Cross-Reference Logic Cross-Reference 2003 Texas Instruments Printed in the U.S.A. by Texoma Business Forms, Durant, Oklahoma Printed on recycled paper. SCYB017A NEW First Revision Logic Cross-Reference

LV00A

Contextual Info: SN54LV00A, 74LV00A QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS389E – SEPTEMBER 1997 – REVISED AUGUST 2002 SN54LV00A . . . J OR W PACKAGE 74LV00A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 1B 1Y

Contextual Info: SN54LV00A, 74LV00A QUADRUPLE 2ĆINPUT POSITIVEĆNAND GATES SCLS389J − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)

MC68XXX

Abstract: CO66 AD0-AD15 CS8900A LAN91C111 PLCC68
Contextual Info: iChip LAN TM iChip LAN CO661AL-L Datasheet Ver. 1.02 International: Connect One Ltd. 2 Hanagar Street Kfar Saba 44425, Israel Tel: +972-9-766-0456 Fax: +972-9-766-0461 E-mail: info@connectone.com http://www.connectone.com Pub. No. 11-3800-01, Copyright February 2003

schematic diagram atx Power supply 500w

Abstract: pioneer PAL 012A 1000w inverter PURE SINE WAVE schematic diagram 600va numeric ups circuit diagrams winbond bios 25064 TLE 9180 infineon smsc MEC 1300 nu TBE schematic diagram inverter 2000w DK55 circuit diagram of luminous 600va UPS
Contextual Info: QUICK INDEX NEW IN THIS ISSUE! Detailed Index - See Pages 3-24 Digital Signal Processors, iCoupler , iMEMS® and iSensor . . . . . 805, 2707, 2768-2769 Connectors, Cable Assemblies, IC Sockets . . . . . . . . . . . 28-568 RF Connectors . . . . . . . . . . . . . . . . . . . . . . Pages 454-455

Contextual Info: 74LV08A QUADRUPLE 2-INPUT AND GATES Description Pin Assignments The 74LV08A provides provides four independent 2-input AND gates with standard push-pull outputs. The device is designed for operation with a power supply range of 2.0V to 5.5V. The inputs are tolerant to 5.5V allowing this device to be used in a

SN74 schmitt trigger

Abstract: SDYU001 SN54LV00A SN54LV02A SN54LV04A SN54LV05A SN54LV08A SN54LV14A SN54LV32A SN54LV74A
Contextual Info: LVC and LV LowĆVoltage CMOS Logic Data Book 1998 Logic Products General Information LVC Gates and MSI LVC Octals LVC Widebus LVC 3.3-V to 5-V Translators and Cable Drivers LV Gates and MSI LV Octals Application Reports Mechanical Data LVC and LV Low-Voltage CMOS Logic

octal Bilateral Switches

Abstract: 74LVC162244A 74LV74 74LVC377
Contextual Info: Philips Semiconductors Advanced Low Voltage CMOS FUNCTION SELECTION GUIDE FUNCTION SELECTION GUIDE LV FAMILY GATES INVERTERS NAND AND NOR FUNCTION DEVICE NUMBER Hex Inverter 74LV04 Hex Inverter unbuffered 74LVUÛ4 Hex Inverter (Schmitt-Trigger) 74LV14 Quad 2-input

74LVC162244A

Abstract: SCHMITT-TRIGGER 3 state 5v tolerant HEX SCHMITT-TRIGGER INVERTER SPICE 74LV74 74LVC377
Contextual Info: Philips Semiconductors Functional Index IC24: ADVANCED LOW VOLTAGE CMOS LOGIC Preface .