74LS21 IC Search Results

7421 pin configuration

Abstract: 7420 pin configuration 74LS20 PIN CONFIGURATION 7421 logic gate 7421 AND 74LS20 function table 74LS21 PIN CONFIGURATION TTL 7420 7421 AND gate PIN CONFIGURATION 7420
Contextual Info: Signehcs I 7420, 7421, LS20, LS21, S20 Gates Logic Products Dual Four-Input NAND '20 AND ('21) Gate Product Specification • TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT (TOTAL) 7420 10ns 8mA 74LS20 10ns 0.8mA 8mA 74S20 3ns 7421 12ns 8mA 74LS21

TTL 74ls21

Abstract: 751A-02 motorola 74ls21
Contextual Info: SN54/74LS21 DUAL 4-INPUT AND GATE DUAL 4-INPUT AND GATE VCC 14 1 LOW POWER SCHOTTKY 13 2 12 11 3 4 10 5 9 6 8 J SUFFIX CERAMIC CASE 632-08 7 14 GND 1 N SUFFIX PLASTIC CASE 646-06 14 1 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN

74ls21 IC

Contextual Info: SANYO SEMICONDUCTOR CORP I EE D LC74HC21 PU 1 im a n n DQoat .33 a CMOS High-Speed Standard Logic LC74HC Series 3003a Dual 4-Input AND Gate E 1743C Features • The LC74HC21 consists of 2 identical 4-input AND gates. • Uses CMOS silicon gate process technology to achieve operating speeds similar to L S -T T L (74LS21 with the

74ls21p

Abstract: 7421 Dual 4-input AND gate 74LS21 74H21 7421 54H21DM 54H21FM 54LS21 54LS21FM 74LS21PC
Contextual Info: 21 C O N N E C T IO N D IA G R A M S P IN O U T A /5 4 /7 4 2 1 54H /74H 21 r / ^54LS/74LS21 ^^ DUAL 4-IN P U T POSITIVE AND GATE O R D E R IN G CO D E: See S e ctio n 9 PIN PKGS OUT C O M M E R C IA L G RADE M ILITA R Y G RADE V c c = + 5.0 V ±5%, T a = 0 °C to + 7 0 ° C

CI 74LS08

Abstract: 7432 TTL fairchild TTL 7421 74LS21 ttl 7432 TTL 74ls32 TTL 7409 TTL 7486 TTL 74ls86 TTL 7432 fairchild
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS D IG IT A L-T T L D16 547408, 54H/74H08, 54S/74S08, 54LS/74LS08 54/7409, 54S/74S09, 54LS/74LS09 D18 54/7411, 54H/74H11, 54S/74S11, 54LS/74LS11, 54S/74S15, 54LS/74LS15 D17 9S41 1^1 FH [iä| [vii Eòi [T| r»1 Vcc Vcc füi

logic diagram of 7432

Abstract: CI 7408 TTL 7486 7408 s.i 7408 FL 9014 7486 nor CI 74LS08 7408 fairchild 7432 TTL
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D16 547408, 54H/74H08, 54S/74S08, 54LS/74LS08 54/7409, 54S/74S09, 54LS/74LS09 D18 54/7411, 54H/74H11, 54S/74S11, 54LS/74LS11, 54S/74S15, 54LS/74LS15 D17 9S41 1^1 FH [iä| [vii Eòi [T| r»1 Vcc Vcc füi Fai np f i ! Föi lyi rn

Contextual Info: SGS-THOMSON *JÆURjflDÊIMJllILiÊTrmDÊi M54HC21 M74HC21 DUAL 4-INPUT AND GATE • HIGH SPEED tpD = 11 ns TYP. at VCc = 5V ■ LOW POWER DISSIPATION Icc = 1 #iA (MAX.) at Ta = 25°C ■ HIGH NOISE IMMUNITY V nih = VN|L = 28“/ o VCC (MIN.) ■ OUTPUT DRIVE CAPABILITY

Contextual Info: TYPES SN54H21, SN54LS21, SN74H21, SN74LS21 DUAL 4-INPUT P0SIT1VE-AND GATES _ REVISED APRIL 1985 SN54H21 . . . JPACKAGE SN54LS21 . . . J OR W PACKAGE S N 74H 21 . . . J OR N PACKAGE SN74LS21 . . . D, J OR N PACKAGE • * Package Options include Both Plastic and

Contextual Info: SbE D • 7 ^ 2 3 ? D 0 3 eJ 7 74 Û12 ■ S G T H r z z S C S -T H O M S O N M 54H C 21 ^ ■ 7 # . ¡ a ffim iC T E iM n ig s _ M 7 4 H C 2 1 S Q S - THOMSON 2 / DUAL 4-INPUT AND GATE ■ HIGH SPEED tpo = 11 ns TYP. at V c c = 5V ■ LOW POWER DISSIPATION

M54HC21

Abstract: M54HC21F1R M74HC21 M74HC21B1R M74HC21C1R M74HC21M1R
Contextual Info: M54HC21 M74HC21 DUAL 4-INPUT AND GATE . . . . . . . . HIGH SPEED tPD = 10 ns TYP. AT VCC = 5 V LOW POWER DISSIPATION ICC = 1 µA (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28% VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE

M54HC21

Abstract: M54HC21F1R M74HC21 M74HC21B1R M74HC21C1R M74HC21M1R
Contextual Info: M54HC21 M74HC21 DUAL 4-INPUT AND GATE . . . . . . . . HIGH SPEED tPD = 10 ns TYP. AT VCC = 5 V LOW POWER DISSIPATION ICC = 1 µA (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28% VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE

TTL 7486

Abstract: FL 9014 TTL 7421 ttl 7432 TTL 7411 TTL 7409 7486 TTL 7411 74LS86 74LS08
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D16 547408, 54H/74H08, 54S/74S08, 54LS/74LS08 54/7409, 54S/74S09, 54LS/74LS09 D18 54/7411, 54H/74H11, 54S/74S11, 54LS/74LS11, 54S/74S15, 54LS/74LS15 D17 9S41 1^1 FH [iä| [vii Eòi [T| r»1 Vcc Vcc füi Fai np f i ! Föi ly i r n

Contextual Info: r z 7 S C S -T H O M S O N Ä 7# M54HC21 M74HC21 DUAL 4-INPUT AND GATE HIGH SPEED tpD = 10 ns TYP. AT Vcc = 5 V LOW POWER DISSIPATION Ice = 1 nA (MAX.) AT Ta = 25 "C HIGH NOISE IMMUNITY Vnih = Vnil = 28% Vcc (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTLLOADS SYMMETRICAL OUTPUT IMPEDANCE

74LS21M

Contextual Info: TYPES SN54H21, SNS4LS21, SN74H21. SN74LS21 DUAL 4-INPUT POSITIVE-AND GATES R E V ISE D APRIL 198B S N 5 4 H 2 1 . . J P A C K A G E Package Options Include Both Plastic and Ceramic Chip Carriers in Addition to Plastic and Ceramic D IP s S N 5 4 L S 2 1 . . J O R W P A C K A G E

74HC21A

Contextual Info: TOSHIBA TC74HC21AP/AF/AFN Dual 4-Input and Gate TheTC 74H C 21A is a high speed CMOS 4-INPUT AND GATE fabricated with silicon gate C 2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation.

Contextual Info: TC74HC21AP/AF/AFN D U A L 4 - l W P U T A N D GATE T h e T C 7 4 H C 2 1 A is a h ig h sp ee d CM O S 4 - I N P U T A N D G A T E fa b r ic a te d w ith s ilic o n g a te C-M O S te c h n o lo g y . It a c h ie v e s th e h ig h sp ee d o p e r a tio n s im i la r to

74LS21

Abstract: DIP14-P-300-2 TC74HC21AF TC74HC21AFN TC74HC21AP CMOS 74LS21
Contextual Info: TOSHIBA TC74HC21AP/AF/AFN TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC74HC21AP, TC74HC21AF, TC74HC21AFN DUAL 4 -INPUT AND GATE Note The JEDEC SOP (FN) is not available in Japan The TC74HC21A is a high speed CMOS 4-INPUT AND GATE fabricated with silicon gate C2MOS technology.

Contextual Info: TO SHIBA TC74HC21AP/AF/AFN TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC74HC21AP, TC74HC21AF, TC74HC21AFN Note The JEDEC SOP (FN) is not available in Japan DUAL 4 -INPUT AND GATE The TC74HC21A is a high speed CMOS 4-INPUT AND GATE fabricated with silicon gate C2MOS technology.

74LS21

Contextual Info: TOSHIBA TC74HC21AP/AF/AFN TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC74HC21AP, TC74HC21AF, TC74HC21AFN Note The JEDEC SOP (FN) is not available in Japan DUAL 4 -IN P U T AND GATE The TC74HC21A is a high speed CMOS 4-INPUT AND GATE fabricated with silicon gate C2MOS technology.

HC 165

Abstract: HC 166 HC167 J122C
Contextual Info: -TC74HC21AP/AF/AFN D U A L 4 -IN P U T A N D GA TE The TC74HC21A is a h ig h speed CMOS 4 -IN P U T A ND G A T E fab ricated w ith silicon g ate C?MOS technology. It achieves the h ig h speed o p eratio n s im ila r to equivalent L ST T L w hile m a in ta in in g the CMOS low pow er

74LS21

Abstract: TR sop-6
Contextual Info: TOSHIBA TC74HC21AP/AF/AFN TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC74HC21AP, TC74HC21AF, TC74HC21AFN Note The JEDEC SOP (FN) is not available in Japan DUAL 4 -IN P U T AND GATE The TC74HC21A is a high speed CMOS 4-INPUT AND GATE fabricated with silicon gate C2MOS technology.

74HC21A

Abstract: 74LS211
Contextual Info: -TC74HC21AP/AF/AFN D U A L 4- IN PU T A ND GATE T h e TC 74H C 21A is a h igh speed CM O S 4 - I N P U T A N D G A T E fa b ric a te d w ith silic o n g a te C2M OS tech n ology. It ach ieves the h igh speed op eratio n s im ila r to equ ivalen t L S T T L w hile m a in ta in in g the CM O S low pow er

IC CMOS 74LS21

Abstract: 74LS21 DIP14-P-300-2 TC74HC21AF TC74HC21AFN TC74HC21AP
Contextual Info: TC74HC21AP/AF/AFN TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC21AP,TC74HC21AF,TC74HC21AFN Dual 4-Input AND Gate The TC74HC21A is a high speed CMOS 4-INPUT AND GATE fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent

IC AND GATE 7408 specification sheet

Abstract: 74LS183 74LS96 SN 74168 7486 XOR GATE IC 74LS192 IC 7402, 7404, 7408, 7432, 7400 IC 7486 for XOR gate IC 74183 74LS193 function table
Contextual Info: PLS-EDIF Bidirectional EDIF Netlist Interface to MAX+PLUS Software Data Sheet September 1991, ver. 3 Features u J Provides a bidirectional netlist interface b etw ee n M A X + P L U S and other m ajor C A E softw are packages Sup ports the industry-standard Electronic Design Interchange Format